Violation of Latency Constraint for Sub Loops - 2022.2 English

Vitis HLS Messaging (UG1448)

Document ID
UG1448
Release Date
2022-12-16
Version
2022.2 English

Description

Warning: [200-894] Latency directive discarded for region %s since it contains subloops.

This message reports that the parent loop contains sub-loops of different latencies.

Explanation

The code is violating latency optimization rules. These sub-loop latencies will be added to the total parent latency as shown in the below code.

The latency of the parent loop = sum(read_a+read_b+read_c) * No of parent loop iterations.

  for (int i = 0; i < iterations; i++)
{
#pragma HLS LOOP_TRIPCOUNT min=c_len/c_n max=c_len/c_n
#pragma HLS LATENCY min=1 max=10
    read_a:
        for (int x = 0; x < N; ++x) {
         #pragma HLS LOOP_TRIPCOUNT min=c_n max=c_n
           #pragma HLS PIPELINE II=1
            result[x] = a[i * N + x];
        }
 
    read_b:
        for (int x = 0; x < N; ++x) {
           #pragma HLS LOOP_TRIPCOUNT min=c_n max=c_n
           #pragma HLS PIPELINE II=1
            result[x] += b[i * N + x];
        }
 
    write_c:
        for (int x = 0; x < N; ++x) {
           #pragma HLS LOOP_TRIPCOUNT min=c_n max=c_n
           #pragma HLS PIPELINE II=1
            c[i * N + x] = result[x];
        }
    }

Solution

When specifying latency constraint to the parent loop, consider taking into account the latency of the sub-loops when applying the latency constraint.