HDMI Receiver Subsystem

Multimedia User Guide (UG1449)

Document ID
UG1449
Release Date
2022-04-21
Revision
1.4 English

The HDMI 1.4/2.0 Receiver Subsystem is a hierarchical IP that bundles a collection of HDMI IP sub-cores and outputs them as a single IP. Xilinx Subsystem IPs are ready-to-use, and do not require the user to assemble sub-cores in order to produce a working system.

Features

  • HDMI 2.0 and 1.4b compatible
  • 2 or 4 symbol/pixel per clock input
  • Supports resolutions up to 4,096 x 2,160 at 60 fps
  • 8, 10, 12, and 16-bit deep color support
  • Dynamic support for RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0 color formats
  • Supports Advanced eXtensible Interface (AXI4)-Stream video input stream and native video input stream
  • Audio support for up to 8 channels
  • High bit rate (HBR) Audio
  • Optional HDCP 2.2/1.4 encryption support
  • Info frames
  • Data Display Channel (DDC)
  • Hot-Plug Detection
  • 3D video support
  • Optional video over AXIS compliant NTSC/PAL support
  • Optional video over AXIS compliant YUV420 support
  • Optional Hot Plug Detect (HPD) active polarity
  • Optional cable detect active polarity

For more information, refer to the HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236).