Video Display

Multimedia User Guide (UG1449)

Document ID
UG1449
Release Date
2022-04-21
Revision
1.4 English

The IPs that are part of the display pipeline read video frames from memory and send them to a monitor through either the DisplayPort Tx controller inside the PS, the SDI transmitter subsystem through the PL, or the HDMI transmitter subsystem through the PL.

All Display IP utilize the DRM/KMS driver framework. The available DRM / KMS driver can be a subset of the underlying LogiCORE IP.