- The AXI4-Stream input and output ports of the subsystem must
have a bit width that is a multiple of 8 bits, up to a maximum of 128 bits.
- Considerations for Designs with HLS Kernels:
- HLS Kernels must have AXI4-Stream input
and output ports.
- The HLS Kernel should be in free-running mode. This is
accomplished by the including the following pragma in the HLS function:
#pragma HLS INTERFACE ap_ctrl_none
port=return
- For HLS Kernels, the port name in the function signature
must match in both the header file and the source file.
- Considerations for HLS-AIE Designs:
- You can only use HLS Kernel blocks to import C/C++ code
(for PL) to connect with AI Engines.
The blocks from the HLS library are not allowed to connect to and
co-simulate with the AI Engine.
- Ensure the bit width of the HLS Kernel input or output
that connects with the AI Engine matches the PLIO width of the AIE.
- Ensure that there are no extra outputs from the
subsystem that will not be in the hardware implementation, such as debug
outputs to monitor internal signals.
- If multiple HLS Kernel inputs are being driven by the
same signal, the signal multiplexing must occur outside the hardware
subsystem, so there are subsystem inputs for each HLS Kernel input.
- If any of the design inputs are randomized between simulation
runs, the design might appear to fail verification. To resolve this issue, set
the seed of MATLAB's random number generator
to a fixed value (for example,
rng(1)
) before
generating input data.