When you complete the verification in Vitis Model Composer, you can package the design for use in IP integrator.
The HDL block must first be configured to use
Compilation Type of IP
Catalog
(the default generation target). This compilation type will
consolidate all hardware source created from Vitis
Model Composer (RTL + IP + Constraints) into an IP. In addition, you can also use the
button on to the right of the Compilation
Type drop-down menu to change the information that goes along
with the IP. In this case, the default values shown below are used.
When you click the Generate button in the Vitis Model Composer Hub block, the RTL code is generated and packaged along with constraints into an IP.