DDR4 SDRAM Reference Clocks

T1 Telco Accelerator Card User Guide (UG1495)

Document ID: UG1495
Release Date: 2021-12-17
Revision: 1.0 English

Both SoCs require one reference clock for the DDR4 SDRAM memory controller. The reference clocks for these interfaces are detailed in the following table. Both clocks are 300 MHz by default.

Table 1. DDR4 SDRAM Reference Clocks
Signal	Target FPGA Input	I/O Standard	P Pin	N Pin
RF_300MHZ_CLK_DDR	IO_L11P/N_T1U_N8_GC _66	LVDS18	AB7	AB6
MP_300MHZ_CLK_DDR	IO_L14P/N_T2L_N2/3_GC_69	LVDS18	G27	F28