A high-level block diagram of the T1 card card is shown in the following figure.
Figure 1.
T1 card High-Level Block
Diagram
The main features and components of the T1 card are as follows:
- Xilinx ZU19EG MPSoC device targeting 5G fronthaul termination
- Xilinx ZU21DR RFSoC device targeting L1 channel coding
- Dual NOR flash of 2x 256 MB in QSPI mode for Zynq UltraScale+ MPSoC
- Dual NOR flash of 2x 256 MB in QSPI mode for Zynq UltraScale+ RFSoC
- 4 GB of DDR4 programmable logic (PL) memory to each Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC device
- 2 GB of DDR4 processor system (PS) memory to each Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC device
- 100G (MAC-to-MAC) communication link between Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC devices
- Two SFP28 cages supporting up to 25G signaling and pluggable optics
- IEEE 1588 Network Synchronizer timing circuit with PPS in/out connectors
- Satellite controller for IPMI compliant monitoring and telemetry
- Bifurcated x8x8 PCIe Gen 3 x16 link to the host from each FPGA
- FHHL form factor with a 75W power envelope
- x16 standard card form factor (FHHL), single slot (111.15 mm x 167.65 mm)
- Maintenance port for card maintenance and developer access using the DMB II Interface (proprietary, requires Xilinx® DMB II kit)