A conceptual block diagram of the IEEE 1588 implementation on the T1 card card is shown in the following figure.
The Zynq UltraScale+ MPSoC recovers clock information from IEEE 1588 packets on the SFP ports. This clock is fed to an IDT 8A34001 Network Synchronizer which in turn cleans up noise and feeds this clock back to the Zynq UltraScale+ MPSoC. When the reference clocking to the network synchronizer disappears, it enters holdover mode. The holdover time for the card is expected to be in the range of four hours with a phase deviation of 1.5μs. During holdover, the reference clock from the Network Synchronizer is derived from a high accuracy OCXO.
The Network Synchronizer device generates the other clocks on the card, including the reference clocks for the DDR4 SDRAM interfaces, user logic, and the MAC-to-MAC communication between the programmable logic and the I/O interfaces. The clock frequencies are factory programmed, and as such are the default on power-up.