Each SoC requires one reference clock for MAC to MAC interface, and both use a 161.1328125 MHz default reference clock.
Signal | Target FPGA Input | I/O Standard | P Pin | N Pin |
---|---|---|---|---|
RF_161.13MHZ_MAC_CLK | MGTREFCLK0_129 | LVDS18 | T28 | T29 |
MP_161.13MHZ_MAC_CLK | MGTREFCLK0_132 | LVDS18 | M32 | M33 |