SFP28 interfaces are in GTY quads 133 and 134. Both use a 161.1328125 MHz default reference clock. It also recovers clocks from the incoming packets.
The clock outputs are AC coupled with 0.01 uF capacitors. LVDS standard is followed, as shown in the following table.
| Signal | Target FPGA Input | I/O Standard | P Pin | N Pin |
|---|---|---|---|---|
| SFP0_IN_CLK | MGTREFCLK0_133 | LVDS18 | F32 | F33 |
| SFP0_161.13MHZ_CLK | MGTREFCLK0_133 | LVDS18 | H32 | H33 |
| SFP1_IN_CLK | MGTREFCLK0_134 | LVDS18 | B32 | B33 |
| SFP1_161.13MHZ_CLK | MGTREFCLK0_134 | LVDS18 | D32 | D33 |