User Clocks

T1 Telco Accelerator Card User Guide (UG1495)
Document ID
UG1495
Release Date
2021-12-17
Revision
1.0 English

Each SoC has been provided with two user clocks, and both SoCs use a 156.25 MHz default user clock.

Table 1. User Clocks
Signal Target FPGA Input I/O Standard P Pin N Pin
RF_156.25MHZ_CLK1 IO_L11P/N_T1U_N8_GC _65 LVDS18 AK3 AK2
RF_156.25MHZ_CLK2 IO_L12P/N_T1U_N8_GC _65 LVDS18 AJ3 AJ2
MP_156.25MHZ_CLK1 IO_L11P/N_T1U_N8_GC _65 LVDS18 AU17 AU16
MP_156.25MHZ_CLK2 IO_L12P/N_T1U_N8_GC _65 LVDS18 AT19 AU18