Introduction

The Xilinx® T2 Telco accelerator card, shown in the following figure, is a single slot, half height, half length (HHHL) plug-in card. It is compliant with PCI Express® technology, supporting PCIe Gen3 x16 and Gen4 x8 bifurcated rates on the host interface.

Figure 1. T2 Telco Accelerator Card

The card features a 16 nm Zynq® UltraScale+™ RFSoC ZU48DR device supporting the following targeted applications:

• 5G NR physical layer functional offload, including but not limited to:
  • Low-density parity check (LDPC) encoding and decoding
  • Rate matching and dematching
  • Code block (CB) and CB group (CBG) processing with HARQ buffer management logic in lookaside mode
• 4G LTE physical layer functional offload, including but not limited to:
  • Turbo encoding and decoding
  • Rate matching and dematching
  • CB processing with HARQ buffer management in lookaside mode

The T2 card value proposition is in offloading CPU intensive encode and decode computations involving LDPC operations, thereby reducing costly CPU resources. The Zynq UltraScale+ RFSoC has hard IP blocks for SD-FEC (eight SD-FEC cores per device) which can be configured to run LDPC encode and decode operations.