In an embedded design, the primary purpose of the datapath is to capture the dataflow of interest in the system application. For vision processing systems, the dataflow might include incoming data from image sensors (e.g., camera, LiDAR, etc.) that is stored in on-chip and off-chip system memory (e.g., BRAM, UltraRAM, DRAM) to be processed inline. For networking systems, the dataflow might be a protocol bridge between two standards like Ethernet and Interlaken.
The PL accelerators datapath (ingress and egress) is mapped to AXI4-Stream interfaces and control interfaces, which are mapped to memory-mapped AXI interconnect. The control interface enables these accelerators to be controlled by the software stack.
Similarly, the AI Engine accelerators datapath is mapped to the AXI4-Stream interfaces. The AI Engine kernels have a run-time parameter (RTP) interface that enables run-time updates. You can access the RTP feature through the Xilinx run-time (XRT) APIs. The AI Engine also supports global memory access to DDR memory for application-specific buffers.