Embedded system designs require hardware and software co-design that target the embedded processor core, dedicated hardware engine, and programmable logic. Embedded system validation requires system-level debugging using the following Xilinx® and third-party tools:
- Vitis embedded software tools
- Vitis AI Engine debugger
- GNU debugger (GDB)
- Arm® Development Studio (DS-5) debugger
The following table shows the purpose of each tool.
|Debug Tool||Use for|
|Vitis embedded software tools||
|Vitis AI Engine debugger||
|Arm DS-5 debugger||
When designing your accelerators, be aware of the following:
- If your embedded system design includes PL or AI Engine-based hardware accelerator blocks, design your accelerators using the AXI4 memory mapped or AXI4 streaming interface. Most Versal ACAP IP is compatible with these protocols. In addition, adding debug integrated logic analyzer (ILA) IP using the Vitis tools flow is easier than adding ILA with native, non-AXI interfaces.
- To debug the PL accelerator blocks, you must include ILA cores in the design.
- If the accelerator design flow uses the Vitis compiler to link the accelerator blocks to the Vitis platform, you must enter additional command
line arguments in the
v++ -lstage to add ILA cores into the kernel interface.
- To measure and debug accelerator performance, you can add the AXI Performance Monitor (APM) core to the platform. The APM core generates interface trace for AXI4 streaming and memory mapped interfaces, which shows kernel active time, idle time, and stall time. Depending on which block is causing the stall time, you can perform additional debugging focused on that block.