AMD Adaptive Computing documentation is organized around a set of standard design processes to help you find relevant content for your current development task. You can access the AMD Versal™ adaptive SoC design processes on the Design Hubs page. You can also use the Design Flow Assistant to better understand the design flows and find content that is specific to your intended design needs.
- System and Solution Planning
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Identifying the components, performance, I/O, and
data transfer requirements at a system level.
Includes application mapping for the solution to PS,
PL, and AI Engine.
Note: For more information, see the Versal Adaptive SoC Design Guide (UG1273).
For additional methodology information, see the following documents:
- Embedded Software Development
- Creating the software platform from the hardware platform and developing the application code using the embedded CPU. Also covers XRT and Graph APIs. See this link in the AI Engine Tools and Flows User Guide (UG1076).
- AI Engine Development
- Creating the AI Engine graph and kernels, library use, simulation debugging and profiling, and algorithm development. Also includes the integration of the PL and AI Engine kernels. See the AI Engine Tools and Flows User Guide (UG1076) and AI Engine Kernel and Graph Programming Guide (UG1079).
- Hardware, IP, and Platform Development
- Creating the PL IP blocks for the hardware platform, creating PL kernels, functional simulation, and evaluating the AMD Vivado™ timing, resource use, and power closure. Also involves developing the hardware platform for system integration. See the Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387).
- System Integration and Validation
- Integrating and validating the system functional performance, including timing, resource use, and power closure. See the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).
- Board System Design
- Designing a PCB through schematics and board layout. Also involves power, thermal, and signal integrity considerations. See the Versal Adaptive SoC Board System Design Methodology Guide (UG1506).