The Versal architecture offers multiple physical interfaces that can be used to connect a debugger to the DPC. The following table shows the debug interfaces recommended for different use cases.
Note: The various APUs and RPUs of the PS can be debugged via the Arm® CoreSight™ infrastructure that is integrated into the PS. The CoreSight infrastructure is accessible via the JTAG-DAP, HSDP, PL, and PCIe® interfaces. For more information, see this link in the Versal ACAP Technical Reference Manual (AM011).
|Recommended Debug Interface||Debugging Goals||Notes|
||Using JTAG allows low-speed connectivity to all debug cores in the design with no additional design modification|
|JTAG + HSDP (Aurora with SmartLynq+)||
||Using HSDP with the SmartLynq+ module enables debug connectivity that is much faster than JTAG with minimal design modification|