Xilinx recommends that you select clocking resources as one of the first steps of your design, well before pinout selection. Your clocking selections can dictate a particular pinout and can also direct logic placement for that logic. Proper clocking selections can yield superior results. Consider the following:
- Constraint creation, particularly in large devices with high utilization in conjunction with clock planning.
- Manual placement of clocking resources if needed for design closure.
- XPIO SelectIO™ interfaces using XPHY Logic for high-performance I/O Interfaces, which exist at the bottom row of the device and have specific clocking requirements that are met by using the Advanced IO Wizard and the Advanced IO Planner.
- XPIO corner banks that exist below PS and GT resources have limited clocking capability, such as no direct access to BUFGCE_DIV and BUFGCTRL resources.
- Additional device-specific functionality that might require up-front planning to avoid issues and take advantage of device features. For information on Versal device features, see this link in the Versal ACAP Clocking Resources Architecture Manual (AM003), Versal ACAP SelectIO Resources Architecture Manual (AM010), and the Inter-byte and Inter-nibble Clocking in an XPIO Bank table in Versal ACAP Packaging and Pinouts Architecture Manual (AM013).
Note: Only GC pins can route to PLL/MMCM. Only XCC pins can be used for Strobes (Capture Clock) for XPHY receive interfaces. Choice of the XCC will determine how many and which XPHY you can reach with the Strobe. See the Inter-byte and Inter-nibble Clocking in an XPIO Bank table in Versal ACAP SelectIO Resources Architecture Manual (AM010) for further information on these rules.