Board designers are faced with a unique task when designing a power distribution system (PDS) for an AMD device. Most other large, dense integrated circuits (such as large microprocessors) come with very specific bypass capacitor requirements. Because these devices are designed only to implement specific tasks in their hardened silicon architecture, their power supply demands are fixed and fluctuate typically within a certain range.
AMD adaptive SoCs do not share this property. Devices can implement an almost infinite number of applications at user-determined frequencies, and in multiple clock domains.
For this reason, it is critical that you understand the power requirements of the design, which you can assess by completing a power estimation using the Power Design Manager (PDM) tool (download at www.xilinx.com/power). Also refer to the PCB Design Guide for your device to fully understand the PDS placement and generic decoupling requirements prior to a power estimation.
Key factors to consider during PDS design include:
- Selecting the right voltage regulators to meet the noise and current requirements based on power estimation. For more information, see this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).
- Consolidating power.
PDM tool, you can select
between Full Power Management or Minimum Power Rails using the Solution
selection on the Power Design page.
Power Tip: AMD recommends adding a shunt resistor to allow the power on each rail to be monitored. Alternatively, you can use a PMBus-enabled regulator or current monitoring integrated circuit (IC).
- Setting up the Sysmon power supply (VCCAUX_SMON).
- Running power distribution network (PDN) simulation.
recommended number of decoupling capacitors shown in the PDM tool Power Design page. These numbers are
based on initial assumptions for step load per rail. However, you can edit the
numbers to reflect your individual design to get more accurate
requirements. Running PDN simulations can help to confirm the exact amount
of decoupling capacitors required to guarantee power supplies that are within the
recommended operating range.
Note: Be sure to follow the capacitor placement shown in the Versal Adaptive SoC PCB Design User Guide (UG863).
For more information on PDN simulation, see Simulating FPGA Power Integrity Using S-Parameter Models (WP411).
report_power command can analyze power on a per regulator or voltage
regulator module (VRM) basis to ensure the required current on each rail does not exceed
the intended power delivery system. For more
information, see this link in the
Versal Adaptive SoC System Integration and Validation
Methodology Guide (UG1388).