Overview

SmartLynq+ Module User Guide (UG1514)

Document ID
UG1514
Release Date
2021-03-08
Revision
1.0 English

The Xilinx® SmartLynq+ Module is a high-speed debug and trace module, primarily targeting the Versal™ adaptive compute acceleration platform (ACAP). It drastically improves configuration and trace speed. For trace capture, the SmartLynq+ module is capable of speeds up to 10 Gb/s by means of its high-speed debug port (HSDP), which is 100 times faster than standard JTAG. Faster iterations and repetitive downloads increase development productivity and reduce the design cycle.