The 100G interface is made into 4 x 25G lanes at four ports. Data can be pumped from the PCIe of the Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC using the DPDK pktgen application. The Xilinx QDMA IP core is used for sending or receiving data to or from the host. All 4 x 25G lanes are mapped to queues 1,2,3, and 4 of the QDMA core respectively in the Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC devices. Data transferred from the Zynq UltraScale+ MPSoC reaches the Zynq UltraScale+ RFSoC through this internal interface, and vice versa.