This section lists the dependencies and known issues at this time.
- If a Pktgen test is not properly terminated, a cold restart (that is to say, a power cycle of the server) might be necessary.
- The boot mode does not change from QSPI mode to JTAG mode when a JTAG cable is connected.
- PCIe® remove and rescan operations do not currently work for the T1 card, and might lead to the card malfunctioning.
- QSPI flash programming works in Vivado® Design Suite 2019.1 for Zynq® UltraScale+™ MPSoC, but not for Zynq® UltraScale+™ RFSoC. It works in SDK 2019.1 for both Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC.
- Dynamic configuration of the FPGA bit file over PCAP might not work as expected and might reboot the server.
- Flashing the images to Zynq UltraScale+ RFSoC QSPI using SDK 2019.1 does not work when the Zynq UltraScale+ RFSoC FPGA status is programmed in Vivado and Zynq UltraScale+ RFSoC PCIe® PFs are visible in the host. SDK gets stuck and there might be a warm reboot of the host. A similar issue can be seen with Zynq UltraScale+ MPSoC devices as well.