This document provides hardware and software installation procedures for the T1 Telco accelerator card along with a guide to the T1 skeleton design. The skeleton design is created specifically for the 16 nm Zynq® UltraScale+™ MPSoC and Zynq UltraScale+ RFSoC devices on the T1 card, and provides connections and software to validate the main interfaces of the board.
The Xilinx® T1 Telco accelerator card is a PCI Express® (PCIe) Gen3 x16 compliant card featuring the 16 nm Zynq® UltraScale+™ MPSoC and Zynq UltraScale+ RFSoC devices. The T1 form factor is full height, half length (FHHL) and single slot, with a PCIe Gen 3 x16 interface that is x8x8 bifurcated providing x8 links from the host to each MPSoC and RFSoC device. Target applications for the T1 card include:
- O-RAN fronthaul termination
- 4G LTE and 5G NR high-PHY lookaside acceleration (supporting 3GPP split option 7-2x)
- 5G layer 1 (L1) high-PHY lookaside acceleration
- Optional use of fronthaul ports for a midhaul (F1) interface between distributed and centralized units (DU and CU)
- 4G LTE and 5G NR inline acceleration of L1 functions (supporting 3GPP split option 7-2x) for up to 4TRX
The T1 card turns a standard server into a virtual baseband unit with the performance, low latency, and power efficiency needed for O-RAN 5G deployments. The turnkey solution enables operators, system integrators, and OEMs to get to market quickly and to simplify the deployment of services at the edge.