T1 Skeleton Design on the ZU21 Zynq UltraScale+ RFSoC - 1.0 English

T1 Telco Accelerator Card Installation Guide (UG1518)

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The design on the ZU21DR Zynq UltraScale+ RFSoC has Linux running on the PS Cortex-A53 processors and has connections from the PCIe Gen3 x8 from the host to the different parts of the ZU21. These connections are accomplished through AXI interconnect. These connections are as follows:

  • Processing system and its DDR
  • PL DDR through a MIG DDR controller
  • 100G MAC

The block diagram below shows the connections.

Figure 1. ZU21 Skeleton Design Connections