This document provides hardware and software installation procedures for the T2 Telco accelerator card along with a guide to the T2 skeleton design. The skeleton design is created specifically for the 16 nm Zynq® UltraScale+™ RFSoC device on the T2 card, and provides connections and software to validate the main interfaces of the board.
The Xilinx® T2 Telco accelerator card is a PCI Express® (PCIe) Gen4 x16 compliant card featuring the 16 nm Zynq UltraScale+ RFSoC device. The T2 form factor is half height, half length (HHHL) and single slot, with a PCIe Gen4 x16 interface that is x8x8 bifurcated providing x8 links from the host to the Zynq UltraScale+ RFSoC device. Target applications for the T2 card include the following:
- 4G LTE and 5G NR high-PHY lookaside acceleration (supporting 3GPP split option 7–2x)
- 5G layer 1 (L1) high-PHY lookaside acceleration
- 4G LTE and 5G NR inline acceleration of L1 functions (supporting 3GPP split option 7–2x) for up to 4TRX
The T2 card turns a standard server into a virtual baseband unit with the performance, low latency, and power efficiency needed for O-RAN 5G deployments. The turnkey solution enables operators, system integrators, and OEMs to get to market quickly and to simplify the deployment of services at the edge.