The design on the ZU48DR Zynq UltraScale+ RFSoC has Linux running on the PS Cortex-A53 processors. It also has connections from the PCIe Gen4 x8 interface from the host to the different parts of the ZU48 device. The following connections are accomplished through AXI interconnect:
- The connection between the PS and the PS DDR memory controller
- The connection to the PL DDR through a MIG DDR memory controller
The following block diagram shows the connections.
Figure 1. ZU48 Skeleton Design Connections
