Board Features

The ZCU670 evaluation board features are listed here. Detailed information for each feature is provided in Board Component Descriptions.

• ZU67DR-2, FSVE1156 package
• Form factor: see Board Specifications
• Configuration from:
  • Dual QSPI
  • Micro-SD card
  • USB-to-JTAG bridge
  • PC4 2x7 2 mm JTAG pod flat cable header
• Clocks
  • SI5381 (various frequencies)

    For additional details on this clock, see Table 1, Table 2, and SI5381A 10 Independent Output Any-Frequency Clock Generator U43.

  • CLK104 (various frequencies):

    Optional for DFE. Contact factory for availability.

    • CLK104_PL_CLK
    • CLK104_PL_SYSREF
    • CLK104_AMS_SYSREF
    • CLK104_DAC_REFCLK (direct connect SSMP)
  • 8A34001 IEEE 1588, Synchronous Ethernet (SyncE), and eCPRI clock (various frequencies)

    For additional details on this clock, see Table 1, Table 2, and SI5381A 10 Independent Output Any-Frequency Clock Generator U43.

  • PS_REF_CLK 33.333333...(33 + 1/3 MHz)
  • ADC_CLK_226 (direct connect SSMP)

    For additional details on this clock, see Table 1, Table 2, and Programmable User SI570 Clocks.

  • DAC_CLK_228 (direct connect SSMP)
  • USER_MGT_SI570 (default 156.25 MHz)

    For additional details on this clock, see Table 1, Table 2, and Programmable User SI570 Clocks.

  • USER_SI570_C0 (default 300 MHz)

    For additional details on this clock, see Table 1, Table 2, and Programmable User SI570 Clocks.

  • User SMA clocks

    For more information, see User SMA Clocks.

• PS DDR4 4 GB 64-bit SODIMM
• PL DDR4 C0 I/F 2 GB 32-bit component (4x8-bit)
• PS GTR (bank 505) assignment
  • USB3 (1 GTR)
  • FMCP HSPC DP (3 GTR)
• PL GTY assignment (2 quads, 8 total GTY)
  • 2x2 zSFP+ (4 GTY on bank GTY127)
  • FMCP HSPC DP (4 GTY, bank GTY128)
• PS MIO connectivity
  • PS MIO[0:5, 7:12]: dual QSPI
  • PS MIO[13]: PS_GPIO2
  • PS MIO[14:17]: 2 channels of I2C
  • PS MIO[18:19]: UART0 (1 of 3 FT4232 UART channels)
  • PS MIO[22:23]: PS_PB, PS_LED I/F
  • PS MIO[26]: PMU_INPUT
  • PS MIO[27:30]: SFP[0:3] TX_DISABLE
  • PS MIO[32:37]: PMU_GPO[0:5]
  • PS MIO[38]: PS_GPIO1
  • PS MIO[39:43, 45:51]: SD I/F
  • PS MIO[52:63]: USB3.0
  • PS MIO[64:77]: Ethernet RGMII
• PL I/O connections
  • PL user GPIO pushbutton
  • PL CPU reset pushbutton
  • PL user GPIO LEDs (4)
• Security—PSBATT button battery backup
• SYSMON header
• Operational switches (power on/off, PS_PROG_B, boot mode DIP switch)
• Operational status LEDs (INIT, DONE, PS STATUS, PGOOD)
• Power management
• System controller (MSP430)

The ZCU670 provides a rapid prototyping platform that uses the XCZU67DR-2FSVE1156I device. The ZU67DR contains many useful processor system (PS) hard block peripherals exposed through the multi-use I/O (MIO) interface and a variety of FPGA programmable logic. The following table lists a brief summary of the resources available within the ZU67DR.

Feature set overview, description, and ordering information is provided in the Zynq UltraScale+ RFSoC DFE Data Sheet: Overview (DS883).