The ZCU670 board provides fixed and variable clock sources for the ZU67DR Zynq UltraScale+ RFSoC. The following table lists the source devices for each clock.
| Clock (Net) Name | Frequency | Clock Source |
|---|---|---|
| Fixed Frequency Clocks | ||
| PS_REF_CLK | 33.33 MHz | U130 SI570 I2C PROG. OSC. (0x5D) |
| SI5381_CLK_125 | 125 MHz | U43 SI5381A PROG. CLK GEN (0x76) |
| SI5381_GTR_REFCLK_USB3 | 26 MHz | |
| Programmable Frequency Clocks | ||
| USER_SI570_C0 | 300 MHz (Default) | U47 SI570 I2C PROG. OSC. (0x5D) |
| USER_MGT_SI570_CLOCK | 156.25 MHz (Default) | U48 SI570 I2C PROG. OSC. (0x5D) |
| BUF_GTR_REF_CLK0 | – | U429 SI53340 clock multiplexer |
| BUF_GTR_REF_CLK1 | – | |
| BUF_GTR_REF_CLK3 | – | |
| SI5381_DAC_REFCLK | 122.88 MHz (Default) | U43 SI5381A PROG. CLK GEN (0x76) |
| SI5381_AMS_SYSREF | – | |
| SI5381_PL_SYSREF | – | |
| SI5381_ADC_REFCLK | 122.88 MHz (Default) | |
| SI5381_PL_CLK | 245.76 MHz (Default) | |
| SI5381_SMA_SE | 10 MHz (Default) | |
| ADC_CLK_226 | User-provided source | J8 (P)/J98 (N) SSMP connector |
| DAC_CLK_228 | User-provided source | J99 (P)/J100 (N) SSMP connector |
| Various 8A34001 eCPRI clocks | Various | U409 8A34001 (0x58) |
The following table lists the connections for each clock.
| Clock Source Ref. Des. and Pin | Net Name | I/O Standard |
|---|---|---|
| U130 SI570 I2C PROG. OSC. | ||
| U130.4 | PS_REF_CLK (series R300) | 1 |
| U47 SI570 I2C Prog. Oscillator DDR4 C0 I/F (300 MHz Default) | ||
| U47.4 | USER_SI570_C0_P | LVDS |
| U47.5 | USER_SI570_C0_N | LVDS |
| U48 SI570 I2C PROG. OSC. (156.25 MHz Default) | ||
| U48.4 | USER_MGT_SI570_CLOCK_P | 2 |
| U48.5 | USER_MGT_SI570_CLOCK_N | 2 |
| U43 SI5381A Programmable Clock Generator | ||
| U43.21 | SI5381_DAC_REFCLK_P | 2 |
| U43.20 | SI5381_DAC_REFCLK_N | 2 |
| U43.24 | SI5381_AMS_SYSREF_P | LVDS |
| U43.23 | SI5381_AMS_SYSREF_N | LVDS |
| U43.28 | SI5381_PL_SYSREF_P | LVDS |
| U43.27 | SI5381_PL_SYSREF_N | LVDS |
| U43.35 | SI5381_ADC_REFCLK_P | 2 |
| U43.34 | SI5381_ADC_REFCLK_N | 2 |
| U43.38 | SI5381_GTR_REF_CLK_P | 2 |
| U43.37 | SI5381_GTR_REF_CLK_N | 2 |
| U43.42 | SI5381_PL_CLK_P | LVDS |
| U43.41 | SI5381_PL_CLK_N | LVDS |
| U43.45 | SI5381_GTR_REFCLK_USB3_P | 2 |
| U43.44 | SI5381_GTR_REFCLK_USB3_N | 2 |
| U43.51 | SI5381_CLK_125_P | LVDS |
| U43.50 | SI5381_CLK_125_N | LVDS |
| U43.54 |
SI5381_SMA_SE (undefined on schematic) |
LVCMOS |
| ADC_CLK_226 | ||
| J8 (P) SMA CONN. | ADC_CLK_226_P | See Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) |
| J98 (N) SMA CONN. | ADC_CLK_226_N | See Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) |
| DAC_CLK_228 | ||
| J99 (P) SMA CONN. | DAC_CLK_228_P | See Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) |
| J100 (N) SMA CONN. | DAC_CLK_228_N | See Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) |
| U409 8A34001 eCPRI Clock | ||
| U409.A9 (Q1) | 8A34001_Q1_OUT_P | 2 |
| U409.B9 (Q1) | 8A34001_Q1_OUT_N | 2 |
| U409.A11 (Q2) | 8A34001_Q2_OUT_P | LVDS |
| U409.B11 (Q2) | 8A34001_Q2_OUT_N | LVDS |
| U409.A12 (Q3) | 8A34001_Q3_OUT_P | LVDS |
| U409.B12 (Q3) | 8A34001_Q3_OUT_N | LVDS |
| U409.M8 (Q7) | 8A34001_Q7_OUT_P | 2 |
| U409.L8 (Q7) | 8A34001_Q7_OUT_N | 2 |
| U409.A6 (Q8) | 8A34001_Q8_OUT_P | LVDS |
| U409.B6 (Q8) | 8A34001_Q8_OUT_N | LVDS |
| U409.M6 (Q11) | 8A34001_Q11_OUT_P | 2 |
| U409.L6 (Q11) | 8A34001_Q11_OUT_N | 2 |
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