[Figure 1, callout 16]
The DP83867IRPAP PHY U33 LED interface (LED_0, LED_2) uses the two LEDs embedded in the P1 RJ45 connector bezel. The LED functional description is as shown in the following table.
| Pin Name | Type | Description |
|---|---|---|
| LED_2 | S, I/O, PD |
By default, this pin indicates receive or transmit activity. Additional functionality is configurable by means of LEDCR1[11:8] register bits. Note: This pin is a strap configuration
pin for RGZ devices only.
|
| LED_1 | S, I/O, PD |
By default, this pin indicates that 100BASE-T link is established. Additional functionality is configurable by means of LEDCR1[7:4] register bits. |
| LED_0 | S, I/O, PD |
By default, this pin indicates that link is established. Additional functionality is configurable by means of LEDCR1[3:0] register bits. |
The LED functions can be re-purposed with a LEDCR1 register write available through the PHYs management data interface, MDIO/MDC. LED_2 is assigned to ACT (activity indicator) and LED_0 indicates link established.
LED_1 (100BASE-T link established) is a separate LED DS8 located on the top side of the board near the RJ45 P1 connector (Figure 1, callout 16).
For more Ethernet PHY details, see the TI DS83867 data sheet on the Texas Instruments website.
The detailed RFSoC connections for the feature described in this section are documented in the ZCU670 board XDC file, referenced in Xilinx Design Constraints.