The GTY transceivers in the ZU67DR are grouped into two channels or quads. The reference clock for a quad can be sourced from the quad above or the quad below the GTY quad of interest. The two GTY quads used on the ZCU670 board have the connectivity listed below. The following table shows the MGTY assignments.
ZCU670 ZU67DR-FSVE1156 GTY Mapping | |||
---|---|---|---|
ZU67DR-FSVE1156 | SFP3 | ch3 | GTY Quad 127 |
SFP2 | ch2 | ||
SFP1 | ch1 | ||
SFP0 | ch0 | ||
USER_MGT_REFCLK | refclk1 | ||
8A34001_CLK1 | refclk0 | ||
FMCP_HSPC_DP3 | ch3 | GTY Quad 128 | |
FMCP_HSPC_DP2 | ch2 | ||
FMCP_HSPC_DP1 | ch1 | ||
FMCP_HSPC_DP0 | ch0 | ||
8A34001_Q11_OUT | refclk1 | ||
8A34001_CLK2_IN | refclk0 |
zSFP+
Four MGTs are provided by PL-side MGT banks 127 and 128 for the quad (2x2 connector) zSFP+ interface. Available GTY reference clocks include two sets of clocks to/from IDT 8A34001 U409. Each zSFP+ connector provides an I2C based control interface. This I2C interface is accessible for each individual zSFP+ module through the I2C multiplexer topology on the ZCU670.
For additional information on GTY transceivers, see the UltraScale Architecture GTY Transceivers User Guide (UG578).
The detailed RFSoC connections for the feature described in this section are documented in the ZCU670 board XDC file, referenced in Xilinx Design Constraints.