The ZU67DR RFSoC PL I/O bank voltages on the ZCU670 board are listed in the following table.
| ZU67DR | Power Net Name | Voltage | Connected To |
|---|---|---|---|
| PL Bank 65 | VCC1V2 | 1.2V | PL_DDR4_C0_DQx, MSP430_UCA1, UART2 |
| PL Bank 66 | VCC1V2 | 1.2V | PL_DDR4_C0_Ax, USER_SI570_C0, SI5381_PL_CLK, ADCIO[08:15], DACIO[08:15] |
| PL Bank 67 | VCC1V8 | 1.8V | ADCIO[00:07], DACIO[0:07], SI5381_CLK2_IN, 8A34001_Q3_OUT, SI5381_CLK_125, CLK104_CLK_SPI_MUX_SEL[0:1] |
| PL Bank 88 | VCC1V8 | 1.8V | SYSMON_SDA/SCL, CPU_RESET, GPIO_SW_PL, SI5381_CLK104_MUX_SEL, SI53340_MUX_GT_SEL, SI53340_MUX_GTR_SEL, CLK104_PL_CLK, 8A34001_Q2_OUT, MUX_PL_SYSREF, 8A34001_CLK6_IN, GPIO_LED[0:3], MSP430_GPIO[0:3] |
| PS Bank 500 | VCC1V8 | 1.8V | MIO_LED/PB, UART0, MIO_I2C0/1, PS_GPIO2, QSPI LWR/UPR |
| PS Bank 501 | VCC1V8 | 1.8V | SDIO I/F, PMU_GPO[0:5], SFP[0:3]_TX_DISABLE, PMU_INPUT |
| PS Bank 502 | VCC1V8 | 1.8V | ENET I/F, USB (3.0) I/F |
| PS Bank 503 | VCC1V8 | 1.8V | PS CONFIG I/F, JTAG I/F |
| PS Bank 504 | VCC1V2 | 1.2V | PS_DDR4_SODIMM (64-BIT) I/F |