[Figure 1, callout 18]
I2C bus I2C1 connects RFSoC U1 PS Bank 500, PL bank 89, and system
controller U38 to two I2C switches (TCA9548A U20 and U22). These I2C1 connections
enable I2C communications with various I2C capable target devices. TCA9548A U20 is
pin-strapped to respond to I2C address 0x74
.
TCA9548A U22 is pin-strapped to respond to I2C address 0x75
.
The following figure shows a high-level view of the I2C1 bus connectivity.
The addresses of each target device on the I2C1 U20 and U22 PCA9548A switches are identified in the following tables.
TCA9548A U20 (Addr 0x74) Port | I2C1 Bus Device | Target Device Address |
---|---|---|
0 | EEPROM U16 | 0X54 |
1 | Si5341 Clock U43 | 0x76 |
2 | USER SI5381A C0 Clock U47 | 0X5D |
3 | USER MGT Si570 Clock U48 | 0X5D |
4 | 8A34001 (zSFP ClK Recovery) U409 | 0x5B |
5 | CLK104 Connector J101 | 0x2F |
6 | RFMC LPAF-50 Connector J82 | USER |
7 | No Connection | NA |
TCA9548A U22 (Addr 0x75) Port | I2C1 Bus Device | Target Device Address |
---|---|---|
0 | FMCP HSPC J28 | 0x## |
1 | USER Si570 C1 Clock U130 | 0X5D |
2 | SYSMON U1 BANK 65 | 0x32 |
3 | PS DDR4 SODIMM SKT. J48 | 0x51 |
4 | SFP3 P3 | 0x50 |
5 | SFP2 P2 | 0x50 |
6 | SFP1 P1 | 0x50 |
7 | SFP0 P0 | 0x50 |
For more information on the TCA9548A, TCA6416A, and PCA9544A, see the Texas Instruments website.
The detailed Zynq UltraScale+ RFSoC connections for the feature described in this section are documented in the ZCU670 board XDC file, referenced in Xilinx Design Constraints.