The PS-side GTR transceiver Bank 505 supports USB (3.0). The remainder of the GTR transceivers are connected to the FMC+ connector.
Bank 505 USB0 lane 2 supports the USB0 (USB3.0) interface described in USB 3.0 Transceiver and USB 2.0 ULPI PHY. The PS-side GTR transceiver provides USB 3.0 host-only connectivity. See VITA57.4 FMCP Connector Pinout.
Bank 505 lanes 0, 1, and 3 support FMC+ over J28.
Bank 505 reference clocks are connected to the U43 SI5341A clock generator as described in SI5381A 10 Independent Output Any-Frequency Clock Generator U43.
The detailed RFSoC connections for the feature described in this section are documented in the ZCU670 board XDC file, referenced in Xilinx Design Constraints.