PSMIO

ZCU670 Evaluation Board User Guide (UG1532)
Document ID
UG1532
Release Date
2022-03-30
Revision
1.0 English

The following table provides PS MIO peripheral mapping implemented on the ZCU670 board. See the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more information on PS MIO peripheral mapping.

Table 1. MIO Peripheral Mapping
MIO[0:25] Bank 500 MIO[26:51] Bank 501 MIO[52:77] Bank 502
0 QSPI_LWR 26 PMU IN 52 USB0
1 QSPI_LWR 27 MIO27 SFP3_TX_DISABLE_B 53 USB0
2 QSPI_LWR 28 MIO28 SFP2_TX_DISABLE_B 54 USB0
3 QSPI_LWR 29 MIO29 SFP1_TX_DISABLE_B 55 USB0
4 QSPI_LWR 30 MIO30 SFP0_TX_DISABLE_B 56 USB0
5 QSPI_LWR 31 Not assigned/no connect 57 USB0
6 Not assigned/no connect 32 PMU GPO 58 USB0
7 QSPI_UPR 33 PMU GPO 59 USB0
8 QSPI_UPR 34 PMU GPO 60 USB0
9 QSPI_UPR 35 PMU GPO 61 USB0
10 QSPI_UPR 36 PMU GPO 62 USB0
11 QSPI_UPR 37 PMU GPO 63 USB0
12 QSPI_UPR 38 GPIO 64 GEM3
13 GPIO 39 SD1 65 GEM3
14 I2C0 40 SD1 66 GEM3
15 I2C0 41 SD1 67 GEM3
16 I2C1 42 SD1 68 GEM3
17 I2C1 43 SD1 69 GEM3
18 UART0 44 Not assigned/no connect 70 GEM3
19 UART0 45 SD1 71 GEM3
20 Not assigned/no connect 46 SD1 72 GEM3
21 Not assigned/no connect 47 SD1 73 GEM3
22 GPIO 48 SD1 74 GEM3
23 GPIO 49 SD1 75 GEM3
24 Not assigned/no connect 50 SD1 76 GEM3
25 Not assigned/no connect 51 SD1 77 GEM3