Creating HLS Components - 2023.1 English

Vitis Unified IDE and Common Command-Line Reference Manual (UG1553)

Document ID

UG1553

Release Date

2023-07-17

Version

2023.1 English

The HLS component uses the v++ -c --mode hls compiler command to build the component. The command uses a configuration file command language as described in v++ Mode HLS. You can build your command line as the Vitis IDE does, which is presented below based on the dct HLS component in the Getting Started With Vitis HLS tutorial. The example includes the HLS component, with source files and test bench.

Tip: Locate the Getting Started With Vitis HLS to download the required files.

Running C Simulation

To run the HLS component in C simulation, use the vitis-run command as described in vitis-run Command. The command from the Vitis IDE to run C simulation is as follows:

vitis-run --mode hls --csim --config ./dct/hls_config.cfg --work_dir dct

Where:

--csim specifies the target for the run.
--config specifies a config file with the compiler directives for the build, and to configure the simulator for the run
--work_dir provides a work directory to build the component
Tip: When creating an HLS component from the command line, the --work_dir specified becomes the HLS component folder when opening it in the Vitis IDE. In this case, the parent folder of the --work_dir is the workspace for launching the Vitis IDE. Opening the workspace in the Vitis IDE lets you use the Analysis view to examine the reports from the build and run process.

The contents of a configuration file can vary, but the dct HLS component from the tutorial uses the following commands in the hls_config.cfg file:

part=xczu9eg-ffvb1156-2-e

[hls]
clock=8ns
clock_uncertainty=15%
flow_target=vitis
syn.output.format=rtl
syn.file=./src/dct.cpp
syn.file=./src/dct.h
syn.top=dct
tb.file=./src/dct_coeff_table.txt
tb.file=./src/dct_test.cpp
tb.file=./src/in.dat
tb.file=./src/out.golden.dat
csim.profile=true
syn.directive.pipeline=dct_2d II=4

Note: The hls_config.cfg file above shows a setting for the C simulation tool. Refer to C-Simulation Configuration for more information.

Running C-Synthesis

To build the dct HLS component the v++ command-line will look as follows:

v++ -c --mode hls --config ./dct/hls_config.cfg --work_dir dct

The success of the synthesis command largely depends on the contents of the configuration file. There are a few key required elements, and then there are a number of options that you can specify. From the config file provided above, the required elements are the part, flow_target, syn.file, and syn.top. Of course, if you want to perform simulation, then you must also specify the tb.file command.

The clock and clock_uncertainty are not required, but here are used to override the default values. The syn.directive.pipeline is used to control the pipeline of the dct_2d function during synthesis. The csim.profile command is used to configure the simulator, and does not have an effect during synthesis.

Tip: The syn.output.format=rtl is the default setting. and is used to generate the RTL code from the C/C++ source code. However, to use the RTL code in a down stream process such as a System project in the Vitis IDE, or a hardware design in the AMD Vivado™ Design Suite, you must specify an syn.output.format=ip_catalog or xo.

Running RTL Co-Simulation

To build the AI Engine component for simulation with the x86simulator, the command-line will look as follows:

vitis-run --mode hls --cosim --config ./dct/hls_config.cfg --work_dir dct

The contents of a configuration file can vary, but the dct HLS component from the tutorial uses the following commands in the hls_config.cfg file:

part=xczu9eg-ffvb1156-2-e

[hls]
clock=8ns
clock_uncertainty=15%
flow_target=vitis
syn.output.format=rtl
syn.file=./src/dct.cpp
syn.file=./src/dct.h
syn.top=dct
tb.file=./src/dct_coeff_table.txt
tb.file=./src/dct_test.cpp
tb.file=./src/in.dat
tb.file=./src/out.golden.dat
csim.profile=true
syn.directive.pipeline=dct_2d II=4
cosim.enable_dataflow_profiling=true
cosim.enable_fifo_sizing=true
cosim.trace_level=port
cosim.wave_debug=true

Note: The hls_config.cfg file above shows some of the settings for the C/RTL co-simulation tool. Refer to Co-Simulation Configuration for more information.