Running C Synthesis - 2023.1 English

Make sure the HLS component is active in the Flow Navigator, or select Component to make it the active component in the tool. When the HLS component is the active component, the Flow Navigator enables running C Simulation, C Synthesis, C/RTL Co-simulation, and Implementation to build and analyze the HLS component. To synthesize the HLS component select Run beneath the C SYNTHESIS heading in the Flow Navigator.

Running C synthesis on the HLS component generates the RTL from the C/C++ source code as described in Synthesizing the Code. The synthesis run in the Vitis IDE uses the v++ -c --mode hls command to generate the RTL, using a config file to specify commands as described in v++ Mode HLS.

Specifying the Flow Target and General Settings

The HLS component can be used to create synthesis results for the Vivado IP flow, or the Vitis kernel flow as described in HLS Flow Overview. The flow target determines the default interface ports applied to the IP or kernel as described in Defining Interfaces, and other details of the synthesized design.

Figure 1. HLS Component General Settings

In the figure above the flow_target is currently set for the Vitis Kernel flow. The default here is for the Vivado IP flow. This target is generally set when the HLS component is created, but can be modified as needed.

The part or board can also be specified under the General settings. These options determine the physical device that the C/C++ code will be synthesized for. The selected device can feature hardware resources that expand or restrict the implementation choices of the RTL synthesis.

Finally, the clock period and clock_uncertainty can be specified to define the timing details of the RTL design. These can affect the timing and scheduling of operations in the design as explained in Specifying the Clock Frequency.

These selections result in the following config file entries:

part=xcvc1902-vsva2197-2MP-e-S

[hls]
flow_target=vitis
clock=8ns
clock_uncertainty=15%

Loading Source Files and Identifying the Top Function

Generally the source code for the HLS component is defined or loaded at the time of creation. However, you can bypass that step when creating the component, and then you will need to add the source files prior to synthesizing the design. To add source files to an existing HLS component open the component config file and navigate to the C Synthesis sources section as shown below. This section of the Config Editor lets you add one or more source files, and specify the top function.

Figure 2. HLS Component Synthesis Sources

The C Synthesis sources displays currently added source files, and lets you edit, or delete current source files, add new source files, and add or modify CFLAGS and CSIMFLAGS.

Add item: Select this command to add new source files to the HLS component. This opens a File Browser, and lets you navigate to and select source files to add.
Add CFLAGS or CSIMFLAGS: You can add compilation flags for synthesis (CFLAGS) and for simulation (CSIMFLAGS) to be applied to all source files, or to be added to specific source files. As shown in the figure above, simply add the flags to the appropriate text entry box for Flags common to all files. To add flags for specific source files, select the source file and select Edit item to add the flags, or modify the file name and path.
top: Lets you specify the function to use as the top-level RTL module for synthesis. The top-level module determines the RTL ports that will be added, and which sub-functions to include in the HLS component. This opens the Select Top Function dialog box that displays a list of functions defined in the source files for you to choose the top function.

These selections result in the following config file entries:

[HLS]
syn.file=<path/to/file.cpp>
syn.file_cflags=<path/to/file.cpp>,<cflag>
syn.file_csimflags=<path/to/file.cpp>,<csimflag>
syn.cflags=<cflag for all files>
syn.csimflags=<csimflag for all files>
syn.top=<top function name>

Specifying the Output Format and Output File

Figure 3. HLS Component Synthesis Settings

The output.format for the RTL synthesis results must be specified. The default format is RTL, which lets the tool synthesize the Verilog and VHDL code from the C/C++ source files, but does not generate the Vivado IP or Vitis kernel as an output product. This approach lets you run synthesis quickly without having to generate hardware files at every iteration. However, to use the RTL design in downstream processes like embedded software design, or Application projects, you must generate the hardware files. The flow you are supporting in your design determines the best choice for output format.

The output.file name and location are determined by the tool, and default to the name of the top function specified for the HLS component. However, you can specify the name and location to override the default values.

These selections result in the following config file entries:

[HLS]
syn.output.format=xo
syn.output.file=../../<filename>

Configuring Default Settings

For the HLS component, the Vitis IDE offers a variety of commands that can be used to configure the default settings of the tool for synthesis and simulation. These configuration commands are presented in Config Editor under the heading of C Synthesis as shown in the figure below. Generally these options are documented as presented in the figure, such as Compile Options, Interface Configuration, and RTL Configuration.

Figure 4. HLS Component Default Settings

Assigning Design Directives

As described in HLS Optimization Directives, design directives let you to customize the synthesis results for the source code. Change the directives across multiple synthesis runs to change the results or optimize your design.

Figure 5. HLS Component Directives

When working with design directives in the Config Editor, as shown above, you do not specify the command name because the Vitis IDE adds the config command for you. You add the location and the options for the design directive as shown. In the example above, the syn.directive.array_partition is defined with the location, the array name, type and factor as described in syn.directive.array_partition, while the command is added by the tool.

Note: You can also use pragmas in your source code, rather than directives in your config file. This will have the same result, but also have the added advantage of being stored directly in your source code. Refer to HLS Pragmas for more information.

Some example design directive entries in the config file:

[HLS]
syn.directive.dataflow=dct
syn.directive.array_partition=dct buf_2d_in type=block factor=4
syn.directive.pipeline=dct2d II=4

Run Synthesis

With the key elements of the HLS component defined in the config file you are ready to run Synthesis. Select Run from the Flow Navigator to begin Synthesis. You can track the progress of the synthesis run in the Output window. The transcript for the synthesis run will have the top function name as <component-name>::synthesis.

Figure 6. HLS Component Running Synthesis

After synthesis is complete, you should see the Synthesis finished successfully message at the end of the transcript. You will also see the Reports folder under the Run command populated as shown in the figure above. The reports available after synthesis are as follows:

Summary: reports the command line used and the time stamp on the results.
Synthesis: reports the synthesis results with information on quality of results, HW interfaces, burst transactions and more. Refer to Synthesis Summary for more information.
Function Call Graph: As described in Function Call Graph Viewer.
Schedule Viewer: As described in Schedule Viewer.
Dataflow Viewer: Only available when thesyn.directive.dataflow is used in the design. Refer to Dataflow Viewer for more information.
Kernel Guidance: reports Guidance messages to provide design advice for the source code and synthesis results.