Running C/RTL Co-Simulation - 2023.1 English

Vitis Unified IDE and Common Command-Line Reference Manual (UG1553)

Document ID
UG1553
Release Date
2023-07-17
Version
2023.1 English

Make sure the HLS component is active in the Flow Navigator or select Component to make it the active component in the tool. When the HLS component is the active component, the Flow Navigator enables running C Synthesis, C Simulation, C/RTL Co-simulation, and Implementation to build and analyze the HLS component. For C/RTL Co-simulation of the HLS component select Run beneath the C/RTL COSIMULATION heading in the Flow Navigator. Refer to C/RTL Co-Simulation in Vitis HLS for additional information.

Running Co-simulation on the HLS component requires a test bench, or test bench files, which must be loaded as described in Running C Simulation. Prior to running co-simulation you must also configure the HLS component to support C/RTL co-simulation. Configure the design using the following steps.

Configure the Simulator

You can configure the simulator prior to running simulation using the C/RTL Co-Simulation section of the Config Editor, as shown below.

Figure 1. HLS Component RTL Co-Simulation Settings

These configuration commands let you specify how the simulation should run. The configuration commands include options to identify compiled simulation libraries for third-party simulators (compiled_library_dir), disable binary test vector format (disable_binary_tv), disable deadlock detection (disable_deadlock_detection) or enable random stall testing during simulation (random_stall). These configuration commands are all documented in Co-Simulation Configuration. Refer to that content for more detailed information.

Run C/RTL Co-Simulation

With the C/RTL Co-simulation setup defined in the config file you are ready to select Run from the Flow Navigator to begin simulation. You can track the progress of simulation in the Output window. The transcript for the synthesis run will have the top function name as <component-name>::co_simulation as shown below.

Figure 2. HLS Component Running C/RTL Co-Simulation

The simulation run in the Vitis IDE uses the vitis-run --mode hls --cosim command as described in vitis-run Command. After the simulation is complete you should see the Co_simulation finished successfully message at the end of the transcript. You will also see the Reports folder under the Run command populated as shown in the figure above. The reports available after co-simulation include:

  • Summary: reports the command line used and the time stamp on the results.
  • Cosimulation: reports the synthesis results with information on quality of results, HW interfaces, burst transactions and more. Refer to Synthesis Summary for more information.
  • Timeline Trace: As described in Schedule Viewer.
  • Wave Viewer: As described in Viewing Simulation Waveforms.
  • Function Call Graph: As described in Timeline Trace Viewer.