Programmable LPDDR4 SI570 Clock

VPK120 Evaluation Board User Guide (UG1568)

Document ID
Release Date
1.1 English

[Figure 1, callout 39, 40, 41]

The VPK120 evaluation board has I2C programmable SI570 low-jitter 3.3V LVDS differential oscillators (U248, U3, U4) connected to the GC inputs of U1 DDR4 DIMM interface bank 702, 705, and 708, respectively. The LPDDR4_CLK1_P/N, LPDDR4_CLK2_P/N and LPDDR4_CLK3_P/N series capacitor coupled clock signals are connected to XCVP1202 ACAP U1. At power-up, this clock defaults to an output frequency of 200.000 MHz. User applications or the system controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VPK120 evaluation board reverts this user clock to the default frequency of 200.000 MHz.

  • Programmable oscillator: Skyworks/Silicon Labs SI570BAB000299DG
  • 10 MHz-945 MHz range, 200.000 MHz default
  • I2C address 0x60
  • LVDS differential output, total stability: 61.5 ppm