VPK120 Evaluation Board User Guide (UG1568)

Document ID
Release Date
1.1 English

The Versal ACAP has 48 PL transceivers including 28 GTYP and 20 GTM type transceivers. The following table contains the mapping to hardened features, quads, channel locations, as well as general features.

Table 1. Transceiver Mapping
VPK120 XCVP1202 VSVA2785 GTY/GTM Mapping
[Unused] ch3 GTYP Quad 106 X0Y6 PCIe X0Y1 MRMAC X0Y1 GTM Quad 206 X0Y4 ch3 GTM SMA
[Unused] ch2 ch2 8A34001 1PPS Clocks
[Unused] ch1 ch1 [Unused]
[Unused] ch0 ch0 [Unused]
[Unused] refclk1 refclk1 8A34001 CLK6 IN
[Unused] refclk0 refclk0 8A34001 Q7 OUT
PCIe Lane 0 ch3 GTYP Quad 105 X0Y5 CPM5 DCMAC X0Y0 GTM Quad 205 X0Y3 ch3 QSFPDD1 Lane 1
PCIe Lane 1 ch2 ch2 QSFPDD1 Lane 5
PCIe Lane 2 ch1 ch1 QSFPDD1 Lane 2
PCIe Lane 3 ch0 ch0 QSFPDD1 Lane 6
[Unused] refclk1 refclk1 [Unused]
PCIe Edge Clock 0 refclk0 refclk0 8A34001 Q8 BUF0
PCIe Lane 4 ch3 GTYP Quad 104 X0Y4 CPM5 (HSDP) GTM Quad 204 X0Y2 ch3 QSFPDD1 Lane 3
PCIe Lane 5 ch2 ch2 QSFPDD1 Lane 7
PCIe Lane 6 ch1 ch1 QSFPDD1 Lane 4
PCIe Lane 7 ch0 ch0 QSFPDD1 Lane 8
[Unused] refclk1 refclk1 8A34001 CLK5 IN MUX1
PCIe Edge Clock 1 refclk0 refclk0 8A34001 Q8 BUF1
PCIe Lane 8 ch3 GTYP Quad 103 X0Y3 CPM5 HSC X0Y0 GTM Quad 203 X0Y1 ch3 QSFPDD2 Lane 1
PCIe Lane 9 ch2 ch2 QSFPDD2 Lane 2
PCIe Lane 10 ch1 ch1 QSFPDD2 Lane 3
PCIe Lane 11 ch0 ch0 QSFPDD2 Lane 4
[Unused] refclk1 refclk1 [Unused]
PCIe Edge Clock 2 refclk0 refclk0 8A34001 Q9 BUF0
PCIe Lane 12 ch3 GTYP Quad 102 X0Y2 CPM5 (HSDP) GTM Quad 202 X0Y0 ch3 QSFPDD2 Lane 5
PCIe Lane 13 ch2 ch2 QSFPDD2 Lane 6
PCIe Lane 14 ch1 ch1 QSFPDD2 Lane 7
PCIe Lane 15 ch0 ch0 QSFPDD2 Lane 8
[Unused] refclk1 refclk1 8A34001 CLK5 IN MUX0
PCIe Edge Clock 3 refclk0 refclk0 8A34001 Q9 BUF1
MRMAC X0Y0 GTYP Quad 201 X1Y1 ch3 FMC DP7
ch2 FMC DP6
ch1 FMC DP5
ch0 FMC DP4
refclk1 SI570_BUF1
refclk0 FMCP1_GBTCLK1
PCIe X1Y0 GTYP Quad 200 X1Y0 ch3 FMC DP3
ch2 FMC DP2
ch1 FMC DP1
ch0 FMC DP0
refclk1 SI570_BUF0
refclk0 FMCP1_GBTCLK0