Measuring and Adjusting for Asymmetric Latency

Enhanced PTP User Guide (UG1602)

Document ID
UG1602
Release Date
2022-10-18
Revision
1.0 English

Solarflare™ and Xilinx® timestamping adapters support 1PPS input/output interfaces to allow asymmetry in the network to be measured.

Note: Adapters require an optional PPS bracket kit and cable assembly (product code SOLR‑PPS‑DP10G or SOLR‑PPS‑DP40G) available from Xilinx sales channels.

On a dedicated wire connection between master 1PPS output and slave 1PPS input, the master emits a single pulse every second. The leading edge of each pulse denotes the exact start of a one second period. When the leading edge of a pulse is detected by the slave adapter, firmware on the adapter is able to calculate the offset from its own start of second period.

  • If the initial observed mean 1PPS offset value is a negative value, it means the master→slave path is slower than the slave→master path, therefore the ptp_rx_latency configuration file option on the slave server is used to compensate the receive latency.
  • If the initial observed mean 1PPS offset value is a positive value, it means the slave→master path is slower than the master→slave path, therefore the ptp_tx_latency configuration file option on the slave server is used to compensate the transmit latency.

This 1PPS calibration is only required once when configuring the network and need only be performed on one slave server in each network segment which share a common network path to the PTP master. There is no need for a permanent 1PPS connection to the adapter. Refer to 1PPS in Practice.