Example - 2022.1 English

Xilinx Power Estimator User Guide (UG440)

Document ID
Release Date
2022.1 English

Maximum XOR Toggle rate in a user combinational logic assuming 1024 wide XOR with a depth of 10 levels is as follows:

  • 815% - Worst input
  • 254% - Random input

Maximum XOR Toggle rate in user combination logic assuming 32 wide XOR with a depth of 5 levels:

  • 516% - Worst input
  • 114% - Random input
Important: In all the sheets which do not have a dedicated Clock Enable column make sure you scale the toggle rate to account for any signal which gates this logic. For example, if the data toggle rate is modeled at 50% but the synchronizing clock is enabled 50% of the time, the resulting toggle rate should be 25% (50% x 50%).
Important: To appreciate what 100% toggle rate means, think of a constantly enabled toggle flip-flop (TFF) whose data input is tied High. The T-output of this flip-flop toggles every clock edge. Very few designs could possibly have an average toggle rate that high (100%).
Note: The I/O sheet has a column to specify signal Data Rate. Make sure you adjust the Toggle Rate and Data Rate columns accurately. For example, on an input signal which toggles on both edges of the clock you would enter Toggle Rate = 200% and Data Rate = DDR (Dual Data Rate).