Importing the Power Estimation Results (*.xpe) for UltraScale+ XPE - Power Optimization Status - 2022.1 English

Xilinx Power Estimator User Guide (UG440)

Document ID
Release Date
2022.1 English

For UltraScale+ XPE, when you import a .xpe file from the Vivado Design Suite, the optimization field in the Implementation section of the Summary Tab will display the following status details of power optimization:

Indicates that only the bram_power_opt from opt_design was run for the imported data.
Indicates that the power_opt was not run in Vivado for the imported data (not even in opt_design). This may occur if the bram_power_opt is explicitly skipped in the implementation run.
Indicates that the power_opt_design was run at some stage in the implementation run for the imported data.

The following figure shows the status details of power optimization.

Figure 1. UltraScale+ XPE - Importing Power Estimation (*.xpe) Results
Tip: In 7 series and earlier device families, you will notice resources used are grouped into a minimum set of lines after import. The map report only contains the counts of the various blocks and you will need to set the bit width, data rate, clock, mode, enable, and other configurations on each XPE sheet to match your design.
Tip: The I/O and block RAM sheets are populated based on unique configuration. I/Os are grouped by bus and all block RAMs with the same configuration appear on a single line. If needed, you might therefore need to add additional rows and adjust the counts to group by clock domain, module, or functionality.