Using an I/O Sheet - 2022.1 English

Xilinx Power Estimator User Guide (UG440)

Document ID
Release Date
2022.1 English

With higher switching speeds and capacitive loads, switching I/O power can be a substantial part of the total power consumption of a Xilinx device. Because of this, it is important to accurately define all I/O related parameters. In the I/O sheet XPE helps you calculate the on-chip and, eventually, off-chip power for your I/O interfaces.

XPE provides a Memory Interface Configuration wizard to allow you to quickly enter the important parameters required for an accurate power estimate of the I/Os involved in the device’s interface to external memory. For step-by-step instructions about how to use the wizard to fill out the memory interface information in the I/O sheet, see Memory Interface Configuration Wizard and the I/O Sheet.

The following figure shows the top section of the I/O sheet (for UltraScale and 7 series devices spreadsheet).

Figure 1. I/O Sheet - Top Section (UltraScale Devices)
Figure 2. I/O Sheet - Top Section (7 Series Devices)

The previous two figures illustrate the three main types of information entered on the I/O sheet: IO Settings, Activity, and, if needed, External Termination.

Figure 3. I/O Sheet - Effect of Output Enable Rate on Power Estimates for Inputs, Outputs, and Bidirectional I/Os (7 Series Devices)

The following paragraphs provide more information on how to fill in each of these columns.

I/O Settings
I/O Standard
Specify here the expected I/O standard you will use for this interface. Configurations which use the on-chip terminations are shown with a DCI suffix in this drop-down menu. Differential I/O standards have a (pair) suffix. For calculations, XPE assumes the standard VCCO level (for example, 3.3V) that is closest to the nominal listed in the data sheet for that I/O standard.
Note: For Spartan-6 devices, the open drain standards I2C and SMBUS can use a VCCO from 2.7V to 3.45V, with a 3.0V nominal voltage. In XPE these are calculated using a VCCO of 3.3V.
Tip: In 7 series devices, using on-chip terminated standards is a good way to improve the signal integrity of the waveforms seen by the receiver. Because the terminations are embedded inside the Xilinx device, the termination power contributes to raising the device junction temperature. To minimize this power, try using the tri-statable on-chip terminated standards (denoted T DCI) whenever possible.
I/O Direction Columns
Enter the number of Input, Output and Bidir (bidirectional) signals for each I/O interface.
Tip: Enter one pin for each differential I/O pair. For example, if your memory has four differential DQS pairs, enter 4 on the Input Pins column.
I/O Performance Settings
These performance settings, such as I/O LOGIC SERDES or BITSLICE, are family dependent. Enter the configuration in which you expect to program these I/Os.
Important: Typically performance settings increase power consumption. Try enabling these settings only if your I/O interface absolutely requires them.
On-Chip Termination
For Input Term, select the appropriate input termination for the selected I/O standard. Select DIFF_TERM when using the on-chip differential termination, or select UNTUNED_SPLIT_40, 50, or 60 Ω impedance when using the optional on-chip termination in HP banks. In the UltraScale device XPE spreadsheet, you can specify both input and output terminations. For Input Term, select DIFF_TERM when using the on-chip differential termination, or select DCI or uncalibrated termination impedance when using on-chip input termination. For Output Term, select RDRV_40_40, RDRV_48_48 or RDRV_60_60 when using on-chip output termination in HP banks. Set Pre-Emphasis to Yes when using the transmitter pre-emphasis feature.
Enter in the expected activity for each I/O interface in the following columns.
Clock (MHz)
Synchronous signals: Enter the frequency of the clock capturing or generating these signals.

Asynchronous signals: Calculate the equivalent frequency of the signal. For example, if you can determine the signal will toggle (change state) 2 million times per second then enter 1 in this column (when converting signal rate to frequency you need 2 transitions to make a period: the transition from 0 to 1 and the transition from 1 to 0).

Toggle Rate
Synchronous elements: Enter how often compared to the clock this signal is expected to change state. For example, if the data changes every 8 clock cycles on average, enter 12.5% (1/8, converted to a percentage).

Asynchronous elements: As explained in the Clock (MHz) description above, enter the equivalent frequency in the Clock (MHz) column and then enter 100% in this column.

Data Rate
Synchronous elements: Enter DDR if the signal is sampled on both the positive and negative edges of the clock. Enter SDR if the signal is sampled on only one edge of the clock.
Note: When the Data Rate is DDR, the specified toggle rate is doubled internally for power estimation. You must not calculate the toggle rate explicitly for double data rate.
Asynchronous elements and Clocks: Enter Async or Clock.
Output Enable
Input only signals: This column has no effect.

Output and bidirectional signals: Specify for a long period of time how much of this time the output buffer is driving a value (compared to the time the driving buffer is disabled or tri-stated.

Tip: As shown in the previous figure for line 1 and 2, setting Output Enable to 100% is a common mistake which degrades the tool accuracy.
Term Disable
Set DCI or IOB33 OCT to disabled (DCITERMDISABLE) when not in use in the fabric. Enter the percentage of time the DCI or ICT termination is disabled.
IBUF Disable
Set HSTL/SSTL IBUF to low power idle (IBUFDISABLE) when not in use in the fabric. Enter the percentage of time the IBUF is disabled.
Output Load
Enter the power factor for the board and other external capacitance driven by the outputs in the module.
External Termination
When not using the available on-chip termination you can use XPE to calculate the power supplied by the Xilinx device to off-chip components such as external board termination resistor networks. Multiple termination types are supported for I/Os configured as outputs. External input terminations are not supported, because calculations often require details of the driver side but these details are not available to XPE.
Note: Select the Show External Board Termination Settings check box to display these columns and a graphic below the table. The graphic shows the supported Output Termination Topologies, so you can easily understand which column to fill depending on the topology you want to build.
Term. Type
Select the appropriate topology from this drop-down menu.
Some termination schemes require two resistor values while others require only a single value. Refer to the termination graphic then enter the resistor value on the appropriate column. The following figure shows the supported I/O termination topologies in this release.
Figure 4. External I/O Termination Topologies (Virtex-6 and 7 Series Devices)