AMD device families have different
Digital Signal Processing (DSP) blocks with different capabilities. To enter information
in these sheets first review the
7 Series DSP48E1 Slice User Guide
(UG479) or the
UltraScale
Architecture DSP Slice User Guide (UG579) to understand the parameters in
the DSP sheet.
Tip: The
default DSP configuration is assumed to be 27x18 in XPE. The toggle rate must be
scaled accordingly for accurate power estimation. For example, if 18x18 DSP is
expected to toggle 25%, then scale it by 0.86, which is 21.5% and enter into XPE.
Similarly, scale the actual toggle rate by 0.8 for 12x12 configuration.
Tip: DSP slices have
clock enable (CE) ports. When entering data in the Toggle Rate column remember to multiply
your data input toggle rate with the DSP slice clock enable rate. For example, if
random data (typically ~38% data toggle rate) is input into the DSP slice and the
slice is clock enabled only 50% of the time, then the output data toggle rate should
be scaled by the CE rate such that the data toggle rate becomes 19% (38% x 50%). See
the following figure for a Virtex 7 example.
Tip: For families that
have a register within the multiplier (MREG), using this pipeline register helps
lower dynamic power.
Figure 1. DSP48E1 Power Sheet (7 Series Devices) - Effect of Clock, Toggle
Rate, and MREG on Power Estimates