Using the PS Sheet for Zynq-7000 SoC - 2022.1 English

Xilinx Power Estimator User Guide (UG440)

Document ID
Release Date
2022.1 English

The PS has between two and five voltage sources depending on the exact configuration. The VCCO_DDR voltage is dependent on the memory interface selected and the VCCO_MIO0 and VCCO_MIO1 voltages are dependent on the I/O interfaces and standards used in the respective banks.

The PS in the Zynq-7000 SoC Technical Reference Manual (UG585).

The processor used in the PS is a dual core Cortex® -A9 processor. The number of A9 Cores used and their clock frequency (Clock (MHz)) are required information. Processor Load of 50% is for average usage and can be adjusted up or down as needed to reflect the processor loading in a specific design. The 0% setting represents the processor in WFI (Wait for Interrupt) mode. WFI mode disables most of the clocks of CPU keeping the logic powered up. The 100% setting represents the CPU running Dhrystone benchmark. When the CPU runs a loop program that uses every cycle, the load parameter should be set to 80%, to represent less computation than Dhrystone.
There are three PLLs in the PS that must be set to the correct frequency (MHz) when used. By default the Processor and Memory PLLs run at twice their associated clock frequency.
Memory Interface
DDR2, DDR3, DDR3L, and LPDDR2 memory interfaces (Memory Type) are supported in either 16 or 32 bit Data Width. The clock frequency (Clock (MHz)) is half the data rate, because these are all DDR interfaces. The Read Rate and Write Rate represent the usage and can be set to any values that together are less than or equal to 100%. The Data Toggle Rate is the average for the data lines with 50% being random data. The Output Load is the board capacitance and the external termination (External Term) is the far end parallel termination used for the data lines.
I/O Interfaces
The PS supports a variety of standard interfaces (I/O Standard) and some general purpose I/O. There are two I/O banks and all interfaces on a bank must use the same voltage. Available I/O Interfaces, I/O Standards, Number of Interfaces, and I/O Bank placement are represented in the XPE tool.
Figure 1. PS Sheet for Zynq-7000 SoC
AXI Interfaces
The PS side of the AXI interfaces are based on the AXI 3 interface specification. Each interface consists of multiple AXI channels. There are nine AXI interfaces for PS-PL interfacing.
  • AXI_ACP - One cache coherent master port for the PL.
  • AXI_HP - Four high performance/bandwidth master ports for the PL.
  • AXI_GP - Four general purpose ports (two master ports and two slave ports).