7 Series FPGAs Configuration User Guide (UG470)

Document ID: UG470
Release Date: 2023-02-01
Revision: 1.16 English

7 Series FPGAs Configuration User Guide
About This Guide
Guide Contents
Configuration Overview
Overview
7 Series FPGAs Configuration Differences from Previous FPGA Generations
Design Considerations
Configuration Bitstream Lengths
FPGA Configuration Data Source
Master Modes
Slave Modes
JTAG Connection
The Basic Configuration Solution
The Low-Cost Configuration Solution
The High-Speed Option
Protecting the FPGA Bitstream against Unauthorized Duplication
Loading Multiple FPGAs with the Same Configuration Bitstream
Configuration Factors
3D ICs Based on SSI Technology
Configuration Debugging
Configuration Interfaces
Configuration Pins
Configuration Banks Voltage Select
Setting Configuration Options in the Vivado Tools
External Master Configuration Clock (EMCCLK) Option
Serial Configuration Mode
Slave Serial Configuration
Master Serial Configuration
Clocking Serial Configuration Data
SelectMAP Configuration Mode
Single Device SelectMAP Configuration
Microprocessor-Driven SelectMAP Configuration
SelectMAP Data Loading
CSI_B
RDWR_B
CCLK
Continuous SelectMAP Data Loading
Non-Continuous SelectMAP Data Loading
SelectMAP Data Ordering
SelectMAP ABORT
Configuration Abort Sequence Description
Readback Abort Sequence Description
ABORT Status Word
Resuming Configuration or Readback After an Abort
Master SPI Configuration Mode
Master SPI Dual (x2) and Quad (x4) Read Commands
Master SPI Quad (x4)
SPI Densities over 128 Mb
SPI Configuration Timing
Determining the Maximum Configuration Clock Frequency
Power-on Sequence Precautions
Master BPI Configuration Interface
Asynchronous Read Mode Support
Page Mode Support
Synchronous Read Mode Support
Determining the Maximum Configuration Clock Frequency
Power-On Sequence Precautions
JTAG Interface
Boundary-Scan and JTAG Configuration
Introduction
Boundary-Scan for 7 Series Devices Using IEEE Standard 1149.1
Test Access Port (TAP)
Boundary-Scan Timing Parameters
Using Boundary-Scan in 7 Series Devices
Multiple Device Configuration
Boundary-Scan Design Considerations
JTAG Signal Routing
Providing Power
Configuring through Boundary-Scan
Dynamic Reconfiguration Port (DRP)
Dynamic Reconfiguration of Functional Blocks
Background
Overview
FPGA Logic Port Definition
Configuration Details
Configuration Data File Formats
Bus Width Auto Detection
Sync Word
Generating Memory Files
PROM Files for Serial Daisy Chains
PROM Files for SelectMAP Configuration
PROM Files for SPI/BPI Configuration
Bit Swapping
Parallel Bus Bit Order
Delaying Configuration
Configuration Sequence
Setup (Steps 1-3)
Device Power-Up (Step 1)
Clear Configuration Memory (Step 2, Initialization)
Sample Mode Pins (Step 3)
Bitstream Loading (Steps 4-7)
Synchronization (Step 4)
Check Device ID (Step 5)
Load Configuration Data Frames (Step 6)
Cyclic Redundancy Check (Step 7)
Startup (Step 8)
Clocking to End of Startup
I/O Transition at the End of Startup
Using DCI with the Multi-function Configuration Pins
STARTUPE2 Primitive
USRCCLKO
Bitstream Security
Bitstream Encryption
AES Overview
Creating an Encrypted Bitstream
Loading the Encryption Key
Loading Encrypted Bitstreams
Bitstream Encryption and Internal Configuration Access Port (ICAPE2)
Advanced Encryption Standard
VCCBATT
Bitstream Authentication
Overview
Implementation
No On-Chip Key Storage for the HMAC Key is Required
Creating an Authenticated Bitstream
eFUSE
eFUSE Registers
eFUSE Control Register (FUSE_CNTL)
JTAG Instructions
eFUSE Programming
Bitstream Composition
Configuration Memory Frames
Configuration Packets
Packet Types
Type 1 Packet
Type 2 Packet
Configuration Registers
CRC Register (00000)
Frame Address Register (00001)
FDRI Register (00010)
FDRO Register (00011)
Command Register (00100)
Control Register 0 (00101)
MASK Register (00110)
Status Register (00111)
LOUT Register (01000)
Configuration Options Register 0 (01001)
MFWR Register (01010)
CBC Register (01011)
IDCODE Register (01100)
AXSS Register (01101)
Configuration Options Register 1 (01110)
Warm Boot Start Address Register (10000)
Watchdog Timer Register (10001)
Precomputed Readback CRC Register (10011)
Boot History Status Register (10110)
Control Register 1 (11000)
BPI/SPI Configuration Options Register (11111)
Device Identifier and Device DNA
DNA Value
Operation
Extending DNA Length
JTAG Access to Device DNA and Identifier
iMPACT Access to Device Identifier
Readback and Configuration Verification
Preparing a Design for Readback
Persist Option
Readback Command Sequences
Accessing Configuration Registers through the SelectMAP Interface
Configuration Register Read Procedure (SelectMAP)
Configuration Memory Read Procedure (SelectMAP)
Accessing Configuration Registers through the JTAG Interface
Configuration Register Read Procedure (JTAG)
Configuration Memory Read Procedure (1149.1 JTAG)
Verifying Readback Data
Readback Capture
Reconfiguration and MultiBoot
Fallback MultiBoot
Overview
Golden Image Initial System Setup
Golden Image and MultiBoot Image Design Requirements
Initial MultiBoot Image System Setup
Initial MultiBoot Design Considerations
BPI - Hardware RS Pin Design Considerations
Process Details for MultiBoot and Fallback
IPROG
WBSTAR Register
Watchdog Timer
RS Pins
IPROG Reconfiguration
IPROG Using ICAPE2
IPROG Embedded in the Bitstream
Status Register for Fallback and IPROG Reconfiguration
Watchdog
Configuration Monitor Mode
User Monitor Mode
Design Examples
Readback CRC
SEU Detection
SEU Correction
Multiple FPGA Configuration
Serial Daisy Chain Configuration
Mixed Serial Daisy Chains
Guidelines and Design Considerations for Serial Daisy Chains
Startup Sequencing (GTS)
Connect All DONE Pins
DONE Pin Rise Time
Ganged Serial Configuration
Multiple Device SelectMAP Configuration
Parallel Daisy Chain Configuration
Ganged SelectMAP Configuration
Advanced JTAG Usage
Introduction
JTAG Configuration/Readback
TAP Controller and Architecture
Boundary-Scan Architecture
Boundary Register
Bit Sequence Boundary-Scan Register
Instruction Register
Bypass Register
Device Identification (IDCODE) Register
JTAG Configuration Register
USERCODE Register
USER1, USER2, USER3, and USER4 Registers
BSCANE2 Primitive
Using Boundary-Scan in 7 Series Devices
Configuring through Boundary-Scan
Single Device Configuration
Multiple Device Configuration
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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