Configuration Interfaces

7 Series FPGAs Configuration User Guide (UG470)

Document ID

UG470

Release Date

2023-02-01

Revision

1.16 English

Xilinx® 7 series devices have five configuration interfaces. Each configuration interface corresponds to one or more configuration modes and bus width, shown in Table: 7 Series FPGA Configuration Modes. For detailed interface timing information, see the respective 7 series FPGAs data sheet. Configuration timing is relative to the CCLK at the pin, even in Master modes where the CCLK is generated internally.

Table 2-1: 7 Series FPGA Configuration Modes
Configuration Mode	M[2:0]	Bus Width	CCLK Direction
Master Serial	000	x1	Output
Master SPI	001	x1, x2, x4	Output
Master BPI	010	x8, x16	Output
Master SelectMAP	100	x8, x16	Output
JTAG	101	x1	Not Applicable
Slave SelectMAP	110	x8, x16, x32⁽¹⁾	Input
Slave Serial(2)	111	x1	Input
Notes: 1.The Slave SelectMAP x16 and x32 bus widths do not support AES-encrypted bitstreams. 2.This is the default setting due to internal pull-up resistors on the Mode pins.