The analog inputs of the ADC use a differential sampling scheme to reduce the effects of common-mode noise signals. This common-mode rejection improves the ADC performance in noisy digital environments. Figure 2-4 shows the benefits of a differential sampling scheme. Common ground impedances (R G ) couple noise voltages (switching digital currents) into other parts of a system. These noise signals can be 100 mV or more. For the ADCs, this noise voltage is equivalent to hundreds of LSBs, thus inducing large measurement errors. The differential sampling scheme samples both the signal and any common mode noise voltages at both analog inputs (V P and V N ). The common mode signal is effectively subtracted because the Track-and-Hold amplifier captures the difference between V P and V N or V P minus V N . To take advantage of the high common mode rejection, users need only connect V P and V N in a differential configuration.
The auxiliary analog inputs (VAUXP[15:0] and VAUXN[15:0]) are analog inputs that are shared with regular digital I/O package balls. The auxiliary analog inputs are automatically enabled when the XADC is instantiated in a design, and these inputs are connected on the top level of the design. The auxiliary analog inputs do not require any user-specified constraints or pin locations. They do not require an I/O standard setting to be added to the UCF or in the PlanAhead pinout tool. In the Vivado design tools, an IOSTANDARD must be selected that is compatible for the bank even though the IOSTANDARD does not affect the input programming. All configuration is automatic when the analog inputs are connected to the top level of the design. Only those auxiliary inputs connected in a design are enabled as analog inputs. The XADC auxiliary inputs pins are labeled in UG475, 7 Series FPGAs Packaging and Pinout Product Specifications User Guide [Ref 2] by appending _ADxP_ and _ADxN_ to the I/O name, where x is the auxiliary pair number. For example, the auxiliary input VAUXP[15] could be designated IO_LxxP_xx_AD15P_xx in the pinout specification.
When designated as analog inputs, these inputs are unavailable for use as digital I/Os. If the I/O is used as a digital I/O, it is subject to the specifications of the configured I/O standard. If the I/O is used as an analog input, the input voltage must adhere to the specifications given in the “Analog-to-Digital Converter” section of the respective data sheet.
It is possible to enable any number of auxiliary analog inputs in an I/O bank and use the remaining as digital I/Os. If there is a mixture of analog and digital I/Os in a bank, the I/O bank must be powered by a supply required to meet the specifications of the digital I/O standard in used. The analog input signal should not exceed the I/O bank supply voltage (V CCO ) in this case.
Note: Auxiliary channels 6, 7, 13, 14, and 15 are not supported on Kintex-7 devices. Some auxiliary analog channels might also not be supported in certain Virtex-7, Artix-7, Spartan-7, and Zynq-7000 SoC device package options. Users should consult the package file for the device.
Adjusting the Acquisition Settling Time
The maximum conversion rate specified for the ADC is 1 MSPS or a conversion time of 1 µs. In continuous sampling mode (see Chapter 5, XADC Timing ), 26 ADCCLK cycles are required to acquire an analog signal and perform a conversion. This implies a maximum ADCCLK frequency of 26 MHz. If the ACQ bit has not been set, four ADCCLKs or 150 ns is allowed for the final stages of the acquisition. When using single channel mode, the ACQ bit in configuration register 0[40h] (see Control Registers, page 35 ), or when using the sequencer, the appropriate ACQ bit in the sequencer registers should be set (see ADC Channel Settling Time ( 4Eh and 4Fh ), page 49 ). This “settling” time ensures that the analog input voltage is acquired to a 12-bit accuracy. The settling time can be increased by reducing the ADCCLK frequency or setting the ACQ bit. In the latter case, assuming the 26 MHz maximum clock frequency, the settling time is increased to 380 ns (10 ADCCLK cycles), and the conversion rate would be reduced to 812 kSPS for the same ADCCLK frequency. In event timing mode (see Chapter 5, XADC Timing ), you can initiate the conversion cycle by using CONVST or CONVSTCLK, allowing more control over the acquisition time, if required.
Figure 2-5 illustrates an equivalent analog input circuit for the external analog input channels in both unipolar and bipolar configurations. The analog inputs consist of a sampling switch and a sampling capacitor used to acquire the analog input signal for conversion. During the ADC acquisition phase, the sampling switch is closed, and the sampling capacitor is charged up to the voltage on the analog input. The time needed to charge this capacitor to its final value (±0.5 LSBs at 12 bits) is determined by the capacitance of the sampling capacitor (C SAMPLE ), the resistance of the analog multiplexer circuit (R MUX ), and any external (source) impedance.
The required 12-bit acquisition time (assuming no additional external or source resistance) in bipolar mode for example is approximated by Equation 2-1 .
The time constant 9 is derived from TC = Ln 2(N + m), where N = 12 for a 12-bit system and m = 1 additional resolution bit.
The required 12-bit acquisition time in unipolar mode is approximated by Equation 2-2 .
For the dedicated channel (V P /V N ), the minimum acquisition time (bipolar mode) required is given by Equation 2-3 .
The auxiliary analog channels (such as, VAUXP[15:0] and VAUXN[15:0]) have a much larger R MUX resistance that is approximately equal to 10 k Ω . Equation 2-4 shows the minimum acquisition time in bipolar mode.
Note: Any additional external resistance (for example, the anti-alias filter or resistor divider) increases the acquisition time requirement because of the increased RMUX value in Equation 2-1 . To calculate the new acquisition time, convert any external resistance to a series equivalent resistance value and add to the RMUX resistance specified in Equation 2-3 and Equation 2-4 . For more information and design considerations for driving the ADC inputs, see XAPP795, Driving the Xilinx Analog-to-Digital Converter Application Note [Ref 7] .
When measuring unipolar analog input signals, the ADCs must operate in a unipolar input mode. This mode is selected by writing to configuration register 0 (see Control Registers, page 35 ). When unipolar operation is enabled, the differential analog inputs (V P and V N ) have an input range of 0V to 1.0V. In this mode, the voltage on V P (measured with respect to V N ) must always be positive. Figure 2-6 shows a typical application of unipolar mode. V N is typically connected to a local ground or common mode signal. The common mode signal on V N can vary from 0V to +0.5V (measured with respect to GNDADC). Because the differential input range is from 0V to 1.0V (V P to V N ), the maximum signal on V P is 1.5V. Figure 2-6 shows the maximum signal levels on V N and V P in unipolar mode, measured with respect to analog ground (GNDADC package ball).
Bipolar Input Signals
The analog inputs can accommodate analog input signals that are positive and negative with respect to a common mode or reference. To accommodate these types of signals, the analog input must be configured to bipolar mode. Bipolar mode is selected by writing to configuration register 0 (see Control Registers ). All input voltages must be positive with respect to analog ground (GNDADC).
When bipolar operation is enabled, the differential analog input (V P – V N ) can have a maximum input range of ±0.5V. The common mode or reference voltage should not exceed 0.5V in this case (see Figure 2-7 ).
The bipolar input mode also accommodates inputs signals driven from a true differential source, for example, a balanced bridge. In this case, V N and V P can swing positive and negative relative to a common mode or reference voltage (see Figure 2-8 ). The maximum differential input (V P – V N ) is ±0.5V. With maximum differential input voltages of ±0.5V and assuming balanced inputs on V N and V P , the common mode voltage must lie in the range 0.25V to 0.75V.
The XADC contains a temperature sensor that produces a voltage output proportional to the die temperature. Equation 2-5 shows the output voltage of the temperature sensor.
Where:
k = Boltzmann’s constant = 1.38 x 10 -23 J/K
T = Temperature K (Kelvin) = °C + 273.15
q = Charge on an electron = 1.6 x 10 -19 C
The output voltage of this sensor is digitized by the ADC to produce a 12-bit digital output code (ADC code). Figure 2-9 illustrates the digital output transfer function for this temperature sensor.
For simplification, the temperature sensor plus the ADC transfer function is rewritten as shown in Equation 2-6 .
The temperature measurement result is stored in the status registers at DRP address 00h . Monitoring FPGA on-chip temperature avoids functional and irreversible failures by ensuring critical operating temperatures are not exceeded.
The XADC also includes on-chip sensors that allow a user to monitor the FPGA power-supply voltages using the ADC. The sensors sample and attenuate (by a factor of three) the power supply voltages V CCINT ,V CCAUX , and V CCBRAM on the package power supply balls. On Zynq-7000 SoC devices, the V CCPINT , V CCPAUX , and V CCO_DDR supplies are also monitored.
Figure 2-10 shows the power-supply sensor transfer function after digitizing by the ADC. The power supply sensor can be used to measure voltages in the range 0V to V CCAUX + 5% with a resolution of approximately 0.73 mV. The transfer function for the supply sensor is shown in Equation 2-7 .
The power-supply measurement results for V CCINT ,V CCAUX , and V CCBRAM are stored in the status registers at DRP addresses 01h , 02h , and 06h , respectively. On Zynq-7000 SoC devices, the measurements for V CCPINT , V CCPAUX , and V CCO_DDR are stored in status registers 0Dh , 0Eh , and 0Fh , respectively.
