The automatic channel sequencer sets up a range of predefined operating modes, where several channels (on-chip sensors and external inputs) are used. The sequencer automatically selects the next channel for conversion, sets the averaging, configures the analog input channels, sets the required settling time for acquisition, and stores the results in the status registers based on a once off setting. The sequencer modes are set by writing to the SEQ3, SEQ2, SEQ1, and SEQ0 bits in configuration register 1 (see Table 3-9 ).
The channel sequencer functionality is implemented using eight control registers from addresses 48h to 4Fh on the DRP (see Control Registers, page 35 ). These eight registers can be viewed as four pairs of 16-bit registers. Each pair of registers controls one aspect of the sequencer functionality. Individual bits in each pair of registers (32 bits) enable specific functionality for a particular ADC channel. The four pairs of registers are:
• ADC Channel Selection Registers ( 48h and 49h )
• ADC Channel Averaging ( 4Ah and 4Bh )
• ADC Channel Analog-Input Mode ( 4Ch and 4Dh )
• ADC Channel Settling Time ( 4Eh and 4Fh )
ADC Channel Selection Registers ( 48h and 49h )
The ADC channel selection registers enable and disable a channel in the automatic channel sequencer. The bits for these registers are defined in Table 4-1 and Table 4-2 . The two 16-bit registers are used to enable or disable the associated channels. A logic 1 enables a particular channel in the sequence. The sequence order is fixed starting from the LSB (bit 0) of register 48h and ending with the MSB (bit 15) of register 49h . The behavior of the channel sequencer does change for simultaneous sampling mode and independent ADC mode (see Simultaneous Sampling Mode and Independent ADC Mode , respectively).
|
Sequence Number
|
Bit |
ADC Channel |
Description |
|---|---|---|---|
|
9/12 |
0 |
16 |
VAUXP[0], VAUXN[0] – Auxiliary channel 0 |
|
10/13 |
1 |
17 |
VAUXP[1], VAUXN[1] – Auxiliary channel 1 |
|
11/14 |
2 |
18 |
VAUXP[2], VAUXN[2] – Auxiliary channel 2 |
|
12/15 |
3 |
19 |
VAUXP[3], VAUXN[3] – Auxiliary channel 3 |
|
13/16 |
4 |
20 |
VAUXP[4], VAUXN[4] – Auxiliary channel 4 |
|
14/17 |
5 |
21 |
VAUXP[5], VAUXN[5] – Auxiliary channel 5 |
|
15/18 |
6 |
22 |
VAUXP[6], VAUXN[6] – Auxiliary channel 6 (1) |
|
16/19 |
7 |
23 |
VAUXP[7], VAUXN[7] – Auxiliary channel 7 (1) |
|
17/20 |
8 |
24 |
VAUXP[8], VAUXN[8] – Auxiliary channel 8 |
|
18/21 |
9 |
25 |
VAUXP[9], VAUXN[9] – Auxiliary channel 9 |
|
19/22 |
10 |
26 |
VAUXP[10], VAUXN[10] – Auxiliary channel 10 |
|
20/23 |
11 |
27 |
VAUXP[11], VAUXN[11] – Auxiliary channel 11 |
|
21/24 |
12 |
28 |
VAUXP[12], VAUXN[12] – Auxiliary channel 12 |
|
22/25 |
13 |
29 |
VAUXP[13], VAUXN[13] – Auxiliary channel 13 (1) |
|
23/26 |
14 |
30 |
VAUXP[14], VAUXN[14] – Auxiliary channel 14 (1) |
|
24/27 |
15 |
31 |
VAUXP[15], VAUXN[15] – Auxiliary channel 15 (1) |
|
Notes: 1. Auxiliary channels 6, 7, 13, 14, and 15 are not supported on Kintex-7 devices. Some auxiliary analog channels might also not be supported in certain Virtex-7, Artix-7, Spartan-7, and Zynq-7000 SoC device package options. Users should consult the package file for the device. |
|||
ADC Channel Averaging ( 4Ah and 4Bh )
The ADC channel averaging registers enable and disable the averaging of the channel data in a sequence. The result of a measurement on an averaged channel is generated by using 16, 64, or 256 samples. The amount of averaging is selected by using the AVG1 and AVG0 bits in configuration register 0 (see Control Registers, page 35 ). These registers also have the same bit assignments as the channel sequence registers listed in Table 4-1 and Table 4-2 .
Averaging can be selected independently for each channel in the sequence. When averaging is enabled for some of the channels of the sequence, the EOS is only pulsed after the sequence has completed the amount of averaging selected by using AVG1 and AVG0 bits (see Table 3-8, page 38 ). If a channel in the sequence does not have averaging enabled, its status register is updated for every pass through the sequencer. When a channel has averaging enabled, its status register is only updated after the averaging is complete. An example sequence is Temperature and V AUX [1], where an averaging of 16 is enabled on V AUX [1]. The sequence is Temperature, V AUX [1], Temperature, V AUX [1], ..., Temperature, V AUX [1] for each of the conversions where the temperature status register is updated. The V AUX [1] status register is updated after the averaging of the 16 conversions.
If averaging is enabled for the calibration channel by setting CAVG to a logic 0 (see Control Registers, page 35 ), the coefficients are updated after the first pass through the sequence. Subsequent updates to coefficient registers require 16 conversions before the coefficients are updated. Averaging is fixed at 16 samples for calibration.
ADC Channel Analog-Input Mode ( 4Ch and 4Dh )
These registers are used to configure an ADC channel as either unipolar or bipolar in the automatic sequence (see Analog Inputs, page 21 ). These registers also have the same bit assignments as the channel sequence registers listed in Table 4-1 and Table 4-2 . However, only external analog input channels, such as the dedicated input channels (V P and V N ) and the auxiliary analog inputs (VAUXP[15:0] and VAUXN[15:0]) can be configured in this way. Setting a bit to logic 1 enables a bipolar input mode for the associated channel. Setting a bit to logic 0 (default) enables a unipolar input mode. All internal sensors use a unipolar transfer function.
ADC Channel Settling Time ( 4Eh and 4Fh )
The default settling time for an external channel in continuous sampling mode is four ADCCLK cycles. The settling time is additional acquisition time after the end of a conversion (see Chapter 5, XADC Timing ). However, by setting the corresponding bits (for external channels) to logic 1 in registers 4Eh and 4Fh , the associated channel can have its settling time extended to 10 ADCCLK cycles. The bit definitions (which bits correspond to which external channels) for these registers are the same as the sequencer channel selection shown in Table 4-1 and Table 4-2 .