The XADC uses a full JTAG interface extension to the DRP interface. This allows read/write access to the XADC DRP through the existing on-chip JTAG infrastructure. No instantiation is required to access the DRP interface over JTAG. A boundary-scan instruction (6-bit instruction = 110111 ) called XADC_DRP, added to 7 series FPGAs, allows access to the DRP through the JTAG TAP. All XADC JTAG instructions are 32 bits wide. For more information on the 7 series FPGA boundary-scan instructions and usage, see UG470, 7\ Series FPGAs Configuration User Guide [Ref 3] . Read and Write operations using the XADC JTAG DRP interface are described in the next sections. Users unfamiliar with basic JTAG functionality should become familiar with the JTAG standard (IEEE 1149.1) before proceeding.
Important : In ISE tools, JTAG access can be limited to read only or completely disabled by using the JTAG_XADC: [Enable ¦ Disable ¦ Status_only] BitGen option. If the dedicated PS to XADC interface is used in the Zynq-7000 SoC devices, this external JTAG access is also disabled (see UG585, Zynq-7000 All Programmable SoC Technical Reference Manual [Ref 4] for more details). When using Vivado tools, JTAG access can be adjusted by adding the following to an XDC file:
set_property BITSTREAM.GENERAL.JTAG_XADC <Enable|Disable|StatusOnly> current_design_name
See UG908, Vivado Design Suite User Guide: Programming and Debugging [Ref 8] for more information on device configuration bitstream settings.
Figure 3-5 shows a timing diagram for a write operation to the XADC DRP through the JTAG TAP. The DRP is accessed through the XADC data register (XADC DR). Before the XADC DR is accessed, the instruction register (IR) must first be loaded with the XADC instruction. The controller is placed in the IR-scan mode, and the XADC instruction is shifted to the IR.
After the XADC instruction is loaded, all data register (DR)-scan operations are carried out on the XADC DR. When the data shifted into XADC DR is a JTAG DRP write command, the XADC DRP arbitrator carries out a DRP write. The format of this write command is described in JTAG DRP Commands . The XADC DR contents are transferred to the XADC DRP arbitrator (see DRP Arbitration ) during the Update-DR state. After the Update-DR state, the arbitrator manages the new data transfer to the XADC DRP register. This takes up to ten DRP clock (DCLK) cycles if a DRP access from the FPGA logic is already in progress.
During the Capture-DR phase (just before data is shifted into the XADC DR), DRP data is captured from the arbitrator. Depending on the last JTAG DRP command, this data can be old data, previously written to the DRP, or requested new read data (see XADC DRP JTAG Read Operation ). This captured data is shifted out (LSB first) on DO as the new JTAG DRP command is shifted in. The 16 LSBs of this 32-bit word contain the JTAG DRP data. The 16 MSBs are set to zero.
If multiple writes to the XADC DR are occurring, it might be necessary to idle the TAP controller for several TCK cycles by adding RTI states before advancing to the next write operation (see Figure 3-5 ). If the F DRP_DCLK or F JTAG_TCK are constrained to a fixed frequency, then Equation 3-1 can be used to determine the number of RTI wait cycles required between JTAG transactions. For example, when F DRP_DCLK = 20 MHz and F JTAG_TCK = 25 MHz, 10 RTI states are required.
If the DRP or JTAG clock frequencies can be changed, then it is useful to determine when the design can be run without idle states (RTI = 0). Assuming RTI = 0, and substituting into Equation 3-1 , F DRP_CLK > 3.334 x F JTAG_CLK . For example, when F DRP_CLK = 20 MHz, then F JTAG_TCK < 6.0 MHz when JTAG is used without any idle states.
Where:
RTI = Required number of additional RTI states to ensure arbitration has fully resolved
F JTAG_TCK = Frequency of TCK used for JTAG
F DRP_DCLK = Frequency of DCLK used for XADC DRP interface
Figure 3-6 shows the timing for an XADC DR read operation. The IR should contain the DR-scan operation (XADC_DRP instruction). A JTAG read from the XADC DRP is a two-step operation.
First, the XADC DR is loaded with the read DRP instruction. This instruction is transferred to the arbitrator during the Update-DR state. Then the arbitrator reads the selected DRP register and stores the newly read 16-bit data. This operation takes several DCLK cycles to complete.
During the DR-Capture phase of the next DR-scan operation, newly read data is transferred from the arbitrator to the XADC DR. This 16-bit data (stored in the 16 LSBs of the 32-bit word) is then shifted out on TDO during the subsequent shift operation (see Figure 3-6 ). The timing diagram shows several idle states at the end of the first DR-scan operation, allowing the arbitrator enough time to fetch the XADC DRP data.
As mentioned previously, if the DCLK frequency is significantly faster than the TCK, these idle states might not be required.
Implementing a DR-scan operation before the arbitrator has completed the DRP-read operation results in old DRP data being transferred to the XADC DR during the DR-capture phase.
To ensure reliable operation over all operating clock frequencies, a minimum of 10 Run-Test-Idle (RTI) states should be inserted. Multiple read operations can be pipelined, as shown in Figure 3-6 . Thus, as the result of a read operation is being shifted out of the XADC DR, an instruction for the next read can be shifted in.
The data shifted into the 32-bit XADC DR during a DR-scan operation instructs the arbitrator to carry out a write, read, or no operation on the XADC DRP. Figure 3-7 shows the data format of the JTAG DRP command loaded into the XADC DR. The first 16 LSBs of XADC DR [15:0] contain the DRP register data. For both read and write operations, the address bits XADC DR [25:16] hold the DRP target register address. The command bits XADC DR [29:26] specify a read, write, or no operation (see Table 3-13 ).
|
CMD[3:0] |
Operation |
|||
|---|---|---|---|---|
|
0 |
0 |
0 |
0 |
No operation |
|
0 |
0 |
0 |
1 |
DRP Read |
|
0 |
0 |
1 |
0 |
DRP Write |
|
- |
- |
- |
- |
Not defined |
It is also possible to enable the auxiliary analog input channel preconfiguration of the FPGA, allowing external analog voltages (on the PCB) to be monitored using the JTAG TAP before configuration. The auxiliary channels are enabled by writing 0001h to DRP address 02h . This address lies within the read-only status register address space and normally holds the result of a V CCAUX measurement. However, a write to this address enables the auxiliary inputs. This function only works prior to configuration. After configuration, these inputs must be explicitly instantiated in the design.
Because the DRP registers are accessed from two different ports (interconnect and JTAG TAP), access must be carefully managed. An arbitrator is implemented to manage potential conflicts between the FPGA logic (fabric) and JTAG port. Arbitration is managed on a per transaction basis (a transaction is a single read/write operation to the DRP). The arbitration rules are as follows:
1. A JTAG transaction cannot be interrupted by the FPGA logic. The FPGA logic transaction is queued by the arbitrator until the JTAG transaction has finished, and then the FPGA logic transaction is completed.
2. A JTAG transaction cannot interrupt an FPGA logic transaction already in progress. As soon as the FPGA logic transaction is finished, then the JTAG transaction is completed.
Three status signals help manage access through the interconnect when the JTAG port is also being used: JTAGBUSY, JTAGMODIFIED, and JTAGLOCKED.
JTAGBUSY
JTAGBUSY becomes active during the update phase of a DRP transaction through the JTAG TAP. This signal resets when the JTAG XADC DR transaction is completed. Each read/write to the XADC DR is treated as an individual transaction. If DRP access initiates through the interconnect port when JTAGBUSY is High, then the arbitrator queues this request for a read/write through the FPGA logic. DRDY does not go active until JTAGBUSY transitions Low and the interconnect transaction is completed. A second DRP access through the FPGA logic must not be initiated until the DRDY for the initial access becomes active and indicates the read/write was successful. If an interconnect access is in progress when a JTAG DRP transaction initiates, the interconnect access is completed before the JTAG transaction.
JTAGMODIFIED
Whenever there is a JTAG write (JTAG reads typically occur more often) to any register in the DRP, the application (FPGA) must be notified about the potential change of configuration. Thus, the JTAGMODIFIED signal transitions High after a JTAG write. A subsequent DRP read/write resets the signal.
JTAGLOCKED
In some cases, it is simpler for the JTAG user to take DRP ownership for a period by locking out access through the interconnect. This is useful in a diagnostic situation where a large number of DRP registers are modified through the JTAG TAP. When a JTAGLOCKED request is made, the JTAGLOCKED signal transitions to the active-High state. The signal remains High until the port is unlocked again. No read or write access is possible through the DRP logic port when the JTAGLOCKED signal is High. The JTAGLOCKED signal is activated by writing 0001h to DRP address 00h . The JTAGLOCKED signal is reset by writing 0000h to DRP address 00h .
JTAGLOCKED is also used to indicate when the DRP is ready for a read or write when the DCLK is first connected or when DCLK becomes active again after a period of inactivity. It can take up to 10 DCLK cycles for JTAGLOCKED to go Low after DCLK becomes active.
Note: The XADC automatically switches over to an on-chip clock oscillator if a missing DCLK is detected.
A user reset of the XADC can also be initiated using the JTAG interface. The XADC is reset by writing xxxxh (any 16-bit value) to DRP address 03h . The JTAG reset has the same effect as pulsing the RESET pin.