Sequencer Modes

Sequencer Modes

There are several sequencer modes as defined by Table 3-9, page 39 . These modes are described in this section.

Default Mode

The default mode is enabled by setting the sequence bits to 0 . In this mode of operation, the XADC automatically monitors the on-chip sensors and stores the results in the status registers. Both ADCs are calibrated in this mode and an averaging of 16 samples is applied to all sensors. The XADC operates independently of any other control register settings in this mode. The XADC also operates in default mode after initial power-up and during FPGA configuration. Table 4-3 shows the default sequence for the XADC.

Note: All alarm outputs (ALM[7:0]) except OT are disabled in default mode. ADC calibration is automatically enabled in default mode.

Single Pass Mode

In single pass mode, the sequencer operates for one pass through the sequencer channel select registers ( 48h and 49h ) and then halts. A sequence of channels as selected in these registers is converted. When the sequence bits as shown in Table 3-9, page 39 are set so as to enable the automatic channel sequencer in single pass mode, the sequence starts. The settings in sequencer registers 48h to 4Fh are used to operate the sequence in a user-defined mode of operation. All channels listed in Table 4-1 and Table 4-2 are available to be used in a sequence. For an explanation of the sequencer registers, see Automatic Channel Sequencer . When the single pass is complete, the XADC defaults to Single Channel Mode described at the start of this chapter. Thus the XADC converts the channel selected by bits CH5 to CH0 in Configuration Register 0. Another single pass can be started by writing to the sequence bits again. For example, changing to single channel mode (SEQ = 0x3) and back to single pass mode (SEQ = 0x1) restarts the single pass mode and another sequence begins.

Continuous Sequence Mode

The continuous sequence mode is similar to single pass mode; however, the sequence automatically restarts as long as the mode is enabled.

The channel sequencer registers can also be reconfigured through the DRP at run time. The sequencer must first be disabled by writing to sequence bits SEQ3 to SEQ0 before writing to any of the sequencer channel registers. It is recommended that the XADC is placed in default mode by writing zeros to SEQ0 and SEQ1 while updating these registers. The XADC is automatically reset whenever SEQ3 to SEQ0 are written to. The current status register contents are not reset at this time. Restarting the sequencer by writing to bits SEQ3 to SEQ0 resets all channel averaging.

Simultaneous Sampling Mode

When placed in simultaneous sampling mode, the sequencer automatically sequences through eight pairs of auxiliary analog input channels for simultaneous sampling and conversion as shown in Table 4-4 . This is useful in applications where it is necessary to preserve the phase relationship between two signals.

Auxiliary analog channels 0 to 7 are assigned to ADC A and are nominated as A channels . Auxiliary analog channels 8 to 15 are assigned to ADC B and are nominated as B channels (see Figure 1-1, page 8 ). One A channel and one B channel are always sampled and converted at the same time in simultaneous sampling mode. Table 4-4 shows how A and B pairs are selected using sequencer channel register 49h . Other sequencer registers that define averaging, analog input mode, and settling time are also available for use in this mode.

Channel averaging ( 4Ah and 4Bh ) and analog-input modes ( 4Ch and 4Dh ) can be set on a per channel basis in simultaneous sampling mode. Thus, it is possible to have an A channel configured as unipolar and a B channel configured as bipolar. Bit definitions as shown in Table 4-1 and Table 4-2 apply. The settling time is applied to a channel pair only; thus, setting bit 0 to 1 in register 4Eh sets the settling time to 10 ADCCLKs for both auxiliary channel 0 and channel 8.

The on-chip temperature and power supplies can also be included in the sequence of channels monitored by setting the appropriate bits in sequencer register 48h . The second ADC (ADC B) does not carry out a conversion in simultaneous sampling mode when an internal sensor channel is being converted.

Automatic calibration cannot be enabled in simultaneous sampling mode. The XADC must be placed in default mode or other sequencer mode to carry out a calibration. The ADCs are automatically calibrated on power-up, which is sufficient for most applications.

Timing

The timing for simultaneous sampling mode is identical to other XADC modes (see Chapter 5, XADC Timing ). Because the ADCs run in lock step, both status registers are updated at exactly the same time. Both continuous and event driven timing modes can be used.

Independent ADC Mode

In the independent ADC mode, ADC A is used to implement a fixed “monitoring mode” similar to the default mode except the alarm functions are enabled (see Automatic Alarms, page 56 ). In this mode, the alarm outputs are active, and you must correctly configure the alarm threshold. Like default sequencer mode, the averaging is fixed at 16 samples.

ADC B is available to be used with the external analog input channels only. This mode frees up the second ADC for use in a customer application where only a single ADC is required while maintaining monitoring of the FPGA for reliability, safety, and anti-tamper applications.

Only the dedicated channel and auxiliary analog input channels can be assigned to ADC B in this sequencer mode. The internal channels (sensors) are automatically assigned to ADC A, which automatically monitors these channels and generates alarms based on the user-defined alarm thresholds.

As with simultaneous sampling mode, it is not possible to select an automatic calibration of ADC B in this sequencer mode. ADC A is automatically calibrated in this mode. To carry out a calibration on ADC B and maintain on-chip monitoring, the default sequence mode should be selected. The XADC can then be returned to Independent ADC mode after EOS goes High at least once.

Sequencer Operation

Channel selection for independent ADC mode is defined using sequencer channel registers 48h and 49h (see Table 4-5 and Table 4-6 ). Internal sensor channels are automatically monitored and calibrated and cannot be assigned to the sequence for ADC B by users. Other sequencer registers that define settling time, analog input mode, and averaging remain unchanged.

Timing

The timing in this mode of operation is also the same for both ADCs. ADC A monitors the internal sensors at the same sample rate and mode selected for ADC B. Again, ADC B can be operated in continuous or event mode timing. In the case of event mode timing, internal sensor monitoring also stops if the CONVST signal is stopped. Therefore, care should be taken to ensure periodic pulsing of CONVST even when ADC B is not being used by the application, if constant coverage of the on-chip environment is required.

Timing for continuous and event modes remain the same as shown in Chapter 5, XADC Timing .